NDLI: A standard-cell library suite for deep-deep sub-micron CMOS technologies

Content Provider	IEEE Xplore Digital Library
Author	Bekiaris, D. Papanikolaou, A. Stamelos, G. Soudris, D. Economakos, G. Pekmestzi, K.
Copyright Year	2011
Description	Author affiliation: National Technical University of Athens, School of Electrical and Computer Engineering, Iroon Polytechneiou 9, Zografou, 15780, Athens, Greece (Bekiaris, D.; Papanikolaou, A.; Stamelos, G.; Soudris, D.; Economakos, G.; Pekmestzi, K.)
Abstract	The continuous scaling of CMOS transistor and interconnect geometries brings to light novel challenges regarding the design of VLSI systems in the nanoscale era. On the other hand, most of the forthcoming deep-deep submicron technologies are not yet mature to be used for fabrication. Hence, the development of standard-cell libraries at the nanometer regime is emerging, in order to estimate the behavior of complex systems in short-term technology nodes. In this paper, we introduce a standard-cell library generator flow for sub-65nm nodes, based on scaling rules presented in the literature. Our goal is to create a set of complete standard cell libraries enabling the design of large digital systems in technologies not yet available for fabrication. The generated libraries are compatible with the state-of-the-art industrial tool flows and they have been evaluated by benchmarks of medium and large complexity.
Starting Page	1
Ending Page	6
File Size	463444
Page Count	6
File Format	PDF
ISBN	9781612848990
e-ISBN	9781612849003
DOI	10.1109/DTIS.2011.5941445
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2011-04-06
Publisher Place	Greece
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Characterization Standard-cell Logic gates Libraries CMOS integrated circuits Transistors Hardware design languages Delay Sub-micron
Content Type	Text
Resource Type	Article

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