NDLI: Interconnect design for a 32 nm node technology

Content Provider	IEEE Xplore Digital Library
Author	Deschacht, D.
Copyright Year	2011
Description	Author affiliation: Laboratoire d'Informatique, de Robotique et de Microelectronique de Montpellier LIRMM, Umversité Montpellier II - CNRS - CC 477, 161 rue Ada, 34095 Montpellier Cedex 5, France (Deschacht, D.)
Abstract	When high speed integrated circuits technology scales down from one node to the other, ITRS suggests a reduction in sizes by a factor of around square of 2, and recommends 17% of improvement on performance. But the obtained gain on active devices is foiled by an increase of interconnect propagation delays and critical crosstalk levels in the Back End of Line (BEOL). This issue especially concerns interconnect of the intermediate metal level. Our works are focused on the impact on signal transmission delay along interconnects of decreasing the space and width. To avoid new industrial manufacturing constraints on cost and reliability, this study is performed without modifying process and materials used in the BEOL of CMOS 45 nm IC. We will study interconnects of 50 nm width, with a 50 nm space between lines in accordance with speed and crosstalk levels requirements of CMOS 32 nm BEOL. When it becomes hard to meet all requirements, it is shown that interconnect density constraints should be relaxed to enlarge the scope of application.
Starting Page	1
Ending Page	4
File Size	462914
Page Count	4
File Format	PDF
ISBN	9781612848990
e-ISBN	9781612849003
DOI	10.1109/DTIS.2011.5941410
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2011-04-06
Publisher Place	Greece
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	signal integrity crosstalk Integrated circuit interconnections Crosstalk VLSI interconnect Dielectrics Copper Delay Driver circuits
Content Type	Text
Resource Type	Article

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