NDLI: Low power architecture of motion estimation and efficient intra prediction based on hardware design for H.264

Content Provider	IEEE Xplore Digital Library
Author	Chaouch, H. Dhahri, S. Zitouni, A. Tourki, R.
Copyright Year	2010
Description	Author affiliation: Laboratory of Electronics and Micro-Electronics (LAB-IT06), Faculty of Sciences of Monastir, Tunisia (Chaouch, H.; Dhahri, S.; Zitouni, A.; Tourki, R.)
Abstract	The coding gains of the H.264/AVC video encoder, come from the improvement of the prediction method for intra and inter prediction in goal to achieve best image quality. However, their enormous computation, high complexity and the dissipated power are the main penalties. The approach proposed in this paper invests and exploits the best hardware solution for intra and inter prediction. Intra prediction is based on nine luma modes by using a 4×4 block for predicted MB (macro-block). Inter prediction is based on a novel low power Hardware Adaptive Motion Estimator (HAME), which is essential for the portable systems that integrate the Full Search (FS), the Gradient Search (GS) and the Four Step Search (FSS) algorithms. Our aim is to achieve an acceptable image quality with the reduction of the computational cost by using hardware accelerator. All modules were designed by using Very High Speed Integrated Circuit (VHSIC) and operate with about 350 MHz clock frequency for inter and intra prediction. The Synopsys environments are used and are based on CMOS 45 nm ASIC technology.
Starting Page	1
Ending Page	6
File Size	904382
Page Count	6
File Format	PDF
ISBN	9781424463381
e-ISBN	9781424463404
DOI	10.1109/DTIS.2010.5487604
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2010-03-23
Publisher Place	Tunisia
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Image quality Frequency selective surfaces Image coding Motion estimation Computer architecture Prediction methods Very high speed integrated circuits Hardware Automatic voltage control Computational efficiency
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

Low-complexity intra-prediction for H.264/AVC using pseudo local decoded image

Efficient Intra Mode Selection using Image Structure Tensor for H.264/AVC

High Efficiency Architecture of Fast Block Motion Estimation with Real-Time QFHD on H.264 Video Coding

Low complexity error concealment scheme for intra-frames in H.264/AVC

An adaptive divide-and-predict coding for intra-frame of H.264/AVC

A Multiframe Motion Estimation Architecture for H.264/AVC

Efficient search and mode prediction algorithms for motion estimation in H.264/AVC

Architecture Design of Low Power Integer Motion Estimation for H. 264/AVC

Efficient Motion Estimation Using a Sorting-Based Early Termination Algorithm in H.264 Video Coding

Low power architecture of motion estimation and efficient intra prediction based on hardware design for H.264

Similar Documents

Low-complexity intra-prediction for H.264/AVC using pseudo local decoded image

Efficient Intra Mode Selection using Image Structure Tensor for H.264/AVC

High Efficiency Architecture of Fast Block Motion Estimation with Real-Time QFHD on H.264 Video Coding

Low complexity error concealment scheme for intra-frames in H.264/AVC

An adaptive divide-and-predict coding for intra-frame of H.264/AVC

A Multiframe Motion Estimation Architecture for H.264/AVC

Efficient search and mode prediction algorithms for motion estimation in H.264/AVC

Architecture Design of Low Power Integer Motion Estimation for H. 264/AVC

Efficient Motion Estimation Using a Sorting-Based Early Termination Algorithm in H.264 Video Coding

Low power architecture of motion estimation and efficient intra prediction based on hardware design for H.264