NDLI: Energy/throughput trade-off in a fully asynchronous NoC for GALS-based MPSoC architectures

Content Provider	IEEE Xplore Digital Library
Author	Rahimi, A. Salehi, M.E. Mohammadi, S. Fakhraie, S.M. Azarpeyvand, A.
Copyright Year	2010
Description	Author affiliation: School of Electrical and Computer Engineering, University of Tehran, 14395-515, Iran (Rahimi, A.; Salehi, M.E.; Mohammadi, S.; Fakhraie, S.M.; Azarpeyvand, A.)
Abstract	In this paper we evaluate the compromising effect of energy saving and throughput degradation on a fully asynchronous NoC architecture with regards to the dynamic voltage scaling guidelines. The investigated fully asynchronous NoC architecture is suitable for GALS-based MPSoCs architectures. The introduced architecture is simulated in 90nm CMOS technology with accurate Spice simulations, where the energy/throughput trade-off is reported and analyzed. Our results indicate that, although lower power may also be achieved by dynamic throughput scaling, this technique yields negligible energy saving for our asynchronous NoC. Therefore, we suggest a dynamic voltage scaling for this architecture which can save 40% energy at the expense of 13% throughput degradation.
Starting Page	1
Ending Page	6
File Size	367491
Page Count	6
File Format	PDF
ISBN	9781424463381
e-ISBN	9781424463404
DOI	10.1109/DTIS.2010.5487580
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2010-03-23
Publisher Place	Tunisia
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Degradation Network-on-a-chip Computer architecture Throughput Frequency Dynamic voltage scaling System-on-a-chip Voltage control Clocks Guidelines
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

Dynamic Voltage and Frequency Scaling Architecture for Units Integration within a GALS NoC

History-Based Dynamic Voltage Scaling with Few Number of Voltage Modes for GALS NoC

A Localized Power Control mixing hopping and Super Cut-Off techniques within a GALS NoC

An Asynchronous Power Aware and Adaptive NoC Based Circuit

Design and Implementation of a GALS Adapter for ANoC Based Architectures

A Fine-Grain Variation-Aware Dynamic ${rm Vdd}$-Hopping AVFS Architecture on a 32 nm GALS MPSoC

Automatic Power Regulation Based on an Asynchronous Activity Detection and its Application to ANOC Node Leakage Reduction

NoC frequency scaling with flexible-pipeline routers

Asynchronous Bypass Channels: Improving Performance for Multi-synchronous NoCs

Energy/throughput trade-off in a fully asynchronous NoC for GALS-based MPSoC architectures

Similar Documents

Dynamic Voltage and Frequency Scaling Architecture for Units Integration within a GALS NoC

History-Based Dynamic Voltage Scaling with Few Number of Voltage Modes for GALS NoC

A Localized Power Control mixing hopping and Super Cut-Off techniques within a GALS NoC

An Asynchronous Power Aware and Adaptive NoC Based Circuit

Design and Implementation of a GALS Adapter for ANoC Based Architectures

A Fine-Grain Variation-Aware Dynamic ${rm Vdd}$-Hopping AVFS Architecture on a 32 nm GALS MPSoC

Automatic Power Regulation Based on an Asynchronous Activity Detection and its Application to ANOC Node Leakage Reduction

NoC frequency scaling with flexible-pipeline routers

Asynchronous Bypass Channels: Improving Performance for Multi-synchronous NoCs

Energy/throughput trade-off in a fully asynchronous NoC for GALS-based MPSoC architectures