NDLI: A Multiframe Motion Estimation Architecture for H.264/AVC

Content Provider	IEEE Xplore Digital Library
Author	Chuan-Yu Cho Sheng-Kai Chang Jia-Shung Wang
Copyright Year	2006
Description	Author affiliation: Inst. of Comput. Sci., Nat. Tsing Hua Univ., Hsinchu, Taiwan (Chuan-Yu Cho; Sheng-Kai Chang; Jia-Shung Wang)
Abstract	The huge computational complexity of motion estimation (ME) process of a standard video codec has resulted in numerous researches on ME VLSI architecture designs. Especially, the new features, variable-block-size (VBS) partitions and multiple-reference-frames (MRF), in the H.264/AVC bring new challenges and opportunities. Though many VLSI designs have been proposed to deal with the new VBS ME feature, there is still no efficient solution for reducing the MRF complexity without drably repeating the whole ME modules. In this paper, an efficient MRF architecture based on a VBS merging scheme is presented. Based on the previous merging scheme, the new architecture can support up to 16 reference frames with the same ME component requirements as a simple 16x16 fixed-block-size ME architecture pluses a few merging logics and five memory latch chains. The proposed architecture is pipelining designed to achieve fully hardware utilization, whereas using the least hardware cost with our previous proposed embedded merging scheme.
Starting Page	1357
Ending Page	1360
File Size	4855216
Page Count	4
File Format	PDF
ISBN	1424404800
ISSN	15224880
DOI	10.1109/ICIP.2006.312586
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2006-10-08
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Motion estimation Automatic voltage control Merging Computer architecture Very large scale integration Hardware Computational complexity Code standards Video codecs Logic MPEG Video Coding VLSI H.264/AVC
Content Type	Text
Resource Type	Article

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