NDLI: Power efficient high performance modular hardware accelerator architecture

Content Provider	IEEE Xplore Digital Library
Author	Tan, T.C. Mustaffa, M.T. Teh, C.H. Leow, W.L.
Copyright Year	2011
Description	Author affiliation: Intel Microelectronics (M) Sdn. Bhd, Phase 3 Kawasan Perusahaan Bayan Lepas, 11900, Penang, Malaysia (Teh, C.H.; Leow, W.L.) \|\| School of Electrical & Electronic Engineering, Universiti Sains Malaysia, Engineering Campus, Seberang Perai Selatan, Nibong Tebal, Penang, 14300, Malaysia (Tan, T.C.; Mustaffa, M.T.)
Abstract	This paper discuss about a power management unit (PMU) which will be implemented in a modular hardware accelerator. The PMU aims to achieve power savings without significantly affecting the performance of the hardware accelerator by timely switching the power state of the device depending on the traffic accessing it and its operating state. The main methods used for power management would be clock and power gating. However some degrees of Dynamic Voltage and Frequency Scaling can be easily added. The PMU will also provide certain level of programmability and will be able to operate accordingly with the software or driver. The functionality of this unit is verified using ABV Verification Test modules.
Starting Page	364
Ending Page	369
File Size	714366
Page Count	6
File Format	PDF
ISBN	9781467300995
e-ISBN	9781467301022
DOI	10.1109/SCOReD.2011.6148766
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2011-12-19
Publisher Place	Malaysia
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	power gating Power demand Logic gates Hardware accelerator clock gating Phasor measurement units Software Hardware power management unit Registers Clocks
Content Type	Text
Resource Type	Article

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