NDLI: Comparative Analysis: Area-Efficient Carry Select Adders 180 Nm Technology

Content Provider	IEEE Xplore Digital Library
Author	Grover, A. Grover, N.
Copyright Year	2013
Description	Author affiliation: SBSSTC Ferozepur, Ferozepur, India (Grover, A.; Grover, N.)
Abstract	This article proposed an area-efficient carry select adder by sharing the common Boolean logic term. Representation of the circuit in summation operation need one XOR gate and one Inverter, while carry out can be represented using one AND gate and an inverter. Using the multiplexer, we are able to select the correct output results according to the carry input signal. In this way, the transistor count in a 32-bit carry select adder can be greatly reduced from 1947 to 960 and the carry select adder performs with a faster speed as compare to the carry ripple adder. Two different design styles using one multiplexer and two multiplexers has also been considered in terms of number of transistors, average power consumption, propagation delay at sum and at carry output.
Starting Page	99
Ending Page	102
File Size	268858
Page Count	4
File Format	PDF
ISBN	9780769551012
DOI	10.1109/AMS.2013.54
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2013-07-23
Publisher Place	China
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Multiplexing Carry Select Adder Power demand Boolean Logic Logic gates Educational institutions Delays Transistors Hardware-Sharing Adders
Content Type	Text
Resource Type	Article

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Comparative Analysis: Area-Efficient Carry Select Adders 180 Nm Technology