NDLI: Design of Vedic-multiplier using area-efficient Carry Select Adder

Content Provider	IEEE Xplore Digital Library
Author	Gokhale, G.R. Bahirgonde, P.D.
Copyright Year	2015
Description	Author affiliation: E&TC Dept., N.K. Orchid Coll. of Eng. & Tech, Solapur, India (Gokhale, G.R.; Bahirgonde, P.D.)
Abstract	In this paper, area-efficient Vedic multiplier is designed using modified Carry Select Adder (CSLA). As the multiplication is nothing but subsequent addition process, adder is important block in the design of multiplier. Simple Ripple Carry adder (RCA) can be used for implementing multiplier. Digital adder has problem of carry propagation, thus carry select adder is used instead. Carry select adder is known to be one of the fastest adder structures. Here novel technique that is Vedic multiplier is implemented instead of normal multipliers like add and shift multiplier, array multiplier etc. Here multiplier is designed based on ancient Vedic multiplication technique. The goal of this paper is to design area-efficient Vedic multiplier based on crosswise and vertical algorithms. Conventional CSLA designs are compared with proposed design to prove its efficiency. On an average, modified CSLA has 29 % less area than Binary to Excess one Converter (BEC) based CSLA for different bit widths. Proposed Vedic multiplier is designed using modified CSLA, which has approximately 10 % less area than BEC based Vedic multiplier. It shows improved performance in terms of area. Proposed design is also compared with the Booth multiplier. Proposed multiplier showed more excellent results than Booth multiplier.
Starting Page	576
Ending Page	581
File Size	324027
Page Count	6
File Format	PDF
ISBN	9781479987900
e-ISBN	9781479987924
DOI	10.1109/ICACCI.2015.7275671
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2015-08-10
Publisher Place	India
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Carry Select Adder Ripple Carry Adder Signal processing algorithms Vedic Multiplier Computer architecture Area-Efficient Binary to Excess one Converter Logic gates Very large scale integration Delays Informatics Adders
Content Type	Text
Resource Type	Article

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