NDLI: ASIC Implementation of One Level 2D-DWT Using Wave-Pipelining

Content Provider	IEEE Xplore Digital Library
Author	Adhinarayanan, V. Paramasivam, R. Gopalakrishnan, S.
Copyright Year	2013
Description	Author affiliation: Dept. of CSE, Sathiyabama Univ., Chennai, India (Adhinarayanan, V.) \|\| Dept. of ECE, Anna Univ., Chennai, India (Paramasivam, R.; Gopalakrishnan, S.)
Abstract	Higher operating frequencies may be obtained in digital systems by using wave-pipelining which permits clock frequencies higher that dictated by largest propagation delay between input and output. This requires proper selection of clock periods and clock skews so as to latch the output of combinational logic circuits at the stable periods. Major contributions of this paper are: proposal for the implementation of one level 2D DWT using lifting scheme by adopting the wave-pipelining technique and proposal for fixing clock frequency and clock skew between the input and output registers of wave-pipelined circuit. For the purpose of evaluating the superiority of the schemes proposed in this paper, the system for the computation of one level 2D DWT is implemented on ASIC using the following techniques: pipelining, non-pipelining and wave-pipelining. From the implementation results, it is observed that the wave pipelined circuit is 1.07 times faster than the non pipelined circuit. The pipelined circuit 1.08 time faster compared to wave pipelined circuit and this is achieved with the increase in area of 1.85 times.
Starting Page	172
Ending Page	175
File Size	172327
Page Count	4
File Format	PDF
ISBN	9780769551012
DOI	10.1109/AMS.2013.56
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2013-07-23
Publisher Place	China
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Application specific integrated circuits Discrete wavelet transforms Registers Field programmable gate arrays Clocks Pipeline processing Application specific Integrated circuits; Discrete wavelet transform; Constant co-efficient multiplier; lifting
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

Implementation of Hybrid Wave-pipelined 2D DWT Using ASIC

ASIC Implementation of one level 2D DWT and 2D DWT in Hybrid Wave-Pipelining & Pipelining

High throughput pipelined 2D Discrete cosine transform for video compression

Evaluation of a Hybrid-Log 2D Wavelet Image Transform

VLSI Architecture of Line-Based Lifting Wavelet Transform for Motion JPEG2000

FPGA Implementation of Wavelet Transform Based on Lifting Scheme

A Novel Architecture for an Efficient Implementation of Image Compression Using 2D-DWT

Design and Implementation of Automated Wave-Pipelined Circuit Using ASIC

Investigation into low power of a 2D inverse discrete cosine transform (IDCT) in FPGAs

ASIC Implementation of One Level 2D-DWT Using Wave-Pipelining

Similar Documents

Implementation of Hybrid Wave-pipelined 2D DWT Using ASIC

ASIC Implementation of one level 2D DWT and 2D DWT in Hybrid Wave-Pipelining & Pipelining

High throughput pipelined 2D Discrete cosine transform for video compression

Evaluation of a Hybrid-Log 2D Wavelet Image Transform

VLSI Architecture of Line-Based Lifting Wavelet Transform for Motion JPEG2000

FPGA Implementation of Wavelet Transform Based on Lifting Scheme

A Novel Architecture for an Efficient Implementation of Image Compression Using 2D-DWT

Design and Implementation of Automated Wave-Pipelined Circuit Using ASIC

Investigation into low power of a 2D inverse discrete cosine transform (IDCT) in FPGAs

ASIC Implementation of One Level 2D-DWT Using Wave-Pipelining