NDLI: Improved single-stage kickback-rejected comparator for high speed and low noise flash ADCs

Content Provider	IEEE Xplore Digital Library
Author	Kazeminia, S. Shino, O. Haghighi, E. Hadidi, K.
Copyright Year	2013
Description	Author affiliation: Dept. of Microelectron. Eng., Urumi Grad. Inst., Urmia, Iran (Kazeminia, S.; Shino, O.; Haghighi, E.; Hadidi, K.)
Abstract	In this paper, the conventional single-stage latched comparator is improved for both high speed and low noise flash ADCs. In the proposed method for high-speed applications, the common mode level of output voltage is preserved unchanged during both amplification and latch operations, to speed up the comparison of small voltage differences. Also, the amplitude of digital control signals is reduced in the modified low noise comparator by using a fully differential structure to remove the concern of digital noise coupling on analog section. Worst-Case simulation results for all corners, using the BSIM3 model of a 0.35μm CMOS process, confirm that a 5mv differential input can be simply detected and recovered to full range values, at 800MS/s and 500MS/s update rate, consuming around 780μW and 650μW in high speed and low noise comparators, respectively. This is equivalent to about 60% improvement in speed of the conventional single-stage comparator. Also, the amplitude of the control signals is reduced to about 18% of full range values, from 3.3v to 0.6v, by using the proposed low noise structure. High speed and low noise comparators can be implemented in $288μm^{2}$ and $480μm^{2}$ active area, respectively.
Starting Page	1
Ending Page	4
File Size	1930755
Page Count	4
File Format	PDF
ISBN	9783000437854
DOI	10.1109/ECCTD.2013.6662323
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2013-09-08
Publisher Place	Germany
Access Restriction	Subscribed
Rights Holder	TU Dresden
Subject Keyword	Latches Power demand Negative feedback Single-Stage Comparator Simulation Noise CMOS process Timing Low Noise Comparator Kickback Noise Rejection High Speed Flash ADCs
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

A 1GS/s low-power low-kickback noise comparator in CMOS process

High-speed low-power Single-Stage latched-comparator with improved gain and kickback noise rejection

A 500 MS/s 600 µW 300 $µm^{2}$ Single-Stage Gain-Improved and Kickback Noise Rejected Comparator in 0.35 µm 3.3 v CMOS Process

High-speed low-kickback-noise accurate comparators based on preamplifier-latch topology

A low-kickback-noise latched comparator for high-speed flash analog-to-digital converters

Design and analysis of novel dynamic latched comparator with reduced kickback noise for high-speed ADCs

A 10-bit 50MS/s pipeline ADC based on kickback-rejected comparators improved for small-amplitude inputs

An improved low-voltage low-power CMOS comparator to be used in high-speed pipeline ADCs

Review on Comparator Design for High Speed ADCs

Improved single-stage kickback-rejected comparator for high speed and low noise flash ADCs

Similar Documents

A 1GS/s low-power low-kickback noise comparator in CMOS process

High-speed low-power Single-Stage latched-comparator with improved gain and kickback noise rejection

A 500 MS/s 600 µW 300 $µm^{2}$ Single-Stage Gain-Improved and Kickback Noise Rejected Comparator in 0.35 µm 3.3 v CMOS Process

High-speed low-kickback-noise accurate comparators based on preamplifier-latch topology

A low-kickback-noise latched comparator for high-speed flash analog-to-digital converters

Design and analysis of novel dynamic latched comparator with reduced kickback noise for high-speed ADCs

A 10-bit 50MS/s pipeline ADC based on kickback-rejected comparators improved for small-amplitude inputs

An improved low-voltage low-power CMOS comparator to be used in high-speed pipeline ADCs

Review on Comparator Design for High Speed ADCs

Improved single-stage kickback-rejected comparator for high speed and low noise flash ADCs