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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Shino, O. Rezaeii, A.B. Moradi, T. |
| Copyright Year | 2014 |
| Description | Author affiliation: Dept. of Microelectron. Eng., Urmia Grad. Inst., Urmia, Iran (Shino, O.; Rezaeii, A.B.; Moradi, T.) |
| Abstract | Implementation of many high-speed systems, such as ADCs, is dependent on high performance comparators. In this paper two structures are presented for high-speed, low-noise and accurate applications. Both of the circuits are based on a positive feedback structure of two back-to-back inverters. First circuit is an improved rail-to-rail folded cascode amplifier in which an active bias circuit is utilized for rearranging the structure appropriate to the running comparison phase. Next circuit is a new comparator which is distinguished by its novel data reception style. In this circuit, PMOS transistors of the latch structure are constructed in separate n-wells, known as hot n-well. Inputs are applied to the bulks of the mentioned PMOS transistors via two differential pairs; hence due to isolation of regenerative outputs from bulks, a sensible attenuation in kickback noise value is observed. Despite the noted advantage, employing hot n-wells enlarges the active area of comparator. Another drawback of the proposed comparator is the necessity of utilizing extra capacitors in its structure. Although the capacitors are negligibly small, their construction should be without any tolerance, otherwise, any mismatch in their structure will enhance the total offset of the circuit. An advantage that can be noted for both presented circuits is the possibility of merging the evaluation phase with reset and latch sequences which leads to an intense increase in comparison speed. The comparators have been simulated using CSMC 0.35μm CMOS process model considering process variations, VDD noise of 100mVp-p, alterations in temperature and applying the inputs for testing the comparators in worst case. Simulation results confirm recognition of a differential input with 2mV pick-to-pick amplitude at as high a clock frequency as 800MHz with power consumption about 2.6mW for first circuit and a 1mV differential input with update rate of 1GHz and power consumption about 1.6mW for the low-noise structure of the second comparator. Layout results of the circuits apprize a 55μm × 13μm and a 24μm × 15μm active area for improved folded cascode comparator and the proposed novel structure respectively. |
| Starting Page | 209 |
| Ending Page | 214 |
| File Size | 4316382 |
| Page Count | 6 |
| File Format | |
| e-ISBN | 9781479944095 |
| DOI | 10.1109/IranianCEE.2014.6999534 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2014-05-20 |
| Publisher Place | Iran |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | High Resolution Comparator Kickback Noise Latches Power demand Noise Capacitors High Speed ADC Inverters Threshold voltage MOS devices High Speed Comparator |
| Content Type | Text |
| Resource Type | Article |
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