NDLI: Analysis and reduction of mismatch in silicon neurons

Content Provider	IEEE Xplore Digital Library
Author	Sun Shuo Basu, A.
Copyright Year	2011
Description	Author affiliation: School of Electrical and Electronic Engineering, Nanyang Technological University, Singapore (Sun Shuo; Basu, A.)
Abstract	In this paper, we describe a methodical approach for reducing errors due to mismatch in neuron circuits. We chose the neuron's current-frequency (f-i) curve as the desired output and use a sensitivity analysis to determine which transistors contribute most significantly to its variation. This allows us to identify the most critical transistors that need to be matched. For the special case in which floating-gate (FG) transistors are used to reduce this mismatch, we propose a method to further reduce the number of FG devices to be used in the circuit resulting in a corresponding reduction in “calibration” time. In addition to reducing mismatch between neurons, the usage of FG devices allows the user to independently set the parameters of each neuron. Since the calibration is based on f-i curve, it can be obtained through address-event representation (AER) circuits that are included in the neuron array for normal functionality. We use one example of commonly used integrate and fire neuron to illustrate this mismatch correction procedure. The method presented allows the corrected neurons to compute both rate codes and spike time codes in a mismatch resilient fashion.
Starting Page	257
Ending Page	260
File Size	337032
Page Count	4
File Format	PDF
ISBN	9781457714696
e-ISBN	9781457714702
DOI	10.1109/BioCAS.2011.6107776
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2011-11-10
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Neurons Layout Programming Threshold voltage Silicon Transistors Arrays
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

Post placement leakage reduction with stress-enhanced filler cells

Measurements and modeling of intrinsic fluctuations in MOSFET threshold voltage

Methodology for analysis of TSV stress induced transistor variation and circuit performance

The optimazation method of device mismatch on 40 nm process technogy

Analysis of Edge Wordline Disturb in multimegabit charge trapping flash NAND arrays

Mismatch reduction through dendritic nonlinearities in a 2D silicon dendritic neuron array

The design of FPGA's high speed configurable logic units

Influence of the organic transistors' layout on electrical parameters

Device mismatch analysis and effect compensation in fundamental analog cells

Analysis and reduction of mismatch in silicon neurons

Similar Documents

Post placement leakage reduction with stress-enhanced filler cells

Measurements and modeling of intrinsic fluctuations in MOSFET threshold voltage

Methodology for analysis of TSV stress induced transistor variation and circuit performance

The optimazation method of device mismatch on 40 nm process technogy

Analysis of Edge Wordline Disturb in multimegabit charge trapping flash NAND arrays

Mismatch reduction through dendritic nonlinearities in a 2D silicon dendritic neuron array

The design of FPGA's high speed configurable logic units

Influence of the organic transistors' layout on electrical parameters

Device mismatch analysis and effect compensation in fundamental analog cells

Analysis and reduction of mismatch in silicon neurons