NDLI: Simulation-based verification of power aware System-on-Chip designs using UPF IEEE 1801

Content Provider	IEEE Xplore Digital Library
Author	Trummer, C. Kirchsteiger, C.M. Steger, C. Weiss, R. Dalton, D. Pistauer, M.
Copyright Year	2009
Description	Author affiliation: CISC Semiconductor Design+Consulting GmbH, Austria (Pistauer, M.) \|\| Institute for Technical Informatics, Graz University of Technology, Austria (Trummer, C.; Kirchsteiger, C.M.; Steger, C.; Weiss, R.) \|\| School of Computer Science and Informatics, University College Dublin, Ireland (Dalton, D.)
Abstract	For System-on-Chips (SoCs) the most critical design constraint is power dissipation. Therefore, power aware design should be introduced at early stages of SoC design where it has the highest benefits for power reduction. This also lowers the design complexity and verification effort. Until recently, capabilities to describe and verify the power design early were inadequate which often led to late re-design. Lately, the IEEE 1801 Standard for Design and Verification of Low Power Integrated Circuits, an extension of the Unified Power Format (UPF) was approved. This work uses the new IEEE 1801 standard to describe power aware design. The power design is automatically translated into an executable hierarchy parallel to the system design. Simulation results from system and power design are used to automatically verify the SoC's power aware design against its specifications.
Starting Page	1
Ending Page	4
File Size	86148
Page Count	4
File Format	PDF
ISBN	9781424443109
e-ISBN	9781424443116
DOI	10.1109/NORCHP.2009.5397836
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2009-11-16
Publisher Place	Norway
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Computer science Computational modeling Computer simulation Circuit simulation Educational institutions Power dissipation System-on-a-chip Informatics Hardware design languages Power integrated circuits
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

Advanced UPF based voltage-aware verification for IOs

Modeling and Simulation of the SDC Data Collection Chip

Verification of Complex Analog and RF IC Designs

Automated simulation-based verification of power requirements for Systems-on-Chips

Formal verification of analog and mixed signal designs

Failing to fail - achieving success in advanced low power design using UPF

SPPV: a new formal verification environment

An Analog-Node Model for VHDL-Based Simulation of RF Integrated Circuits

Formal Interpretation of Assertion-Based Features on AMS Designs

Simulation-based verification of power aware System-on-Chip designs using UPF IEEE 1801

Similar Documents

Advanced UPF based voltage-aware verification for IOs

Modeling and Simulation of the SDC Data Collection Chip

Verification of Complex Analog and RF IC Designs

Automated simulation-based verification of power requirements for Systems-on-Chips

Formal verification of analog and mixed signal designs

Failing to fail - achieving success in advanced low power design using UPF

SPPV: a new formal verification environment

An Analog-Node Model for VHDL-Based Simulation of RF Integrated Circuits

Formal Interpretation of Assertion-Based Features on AMS Designs

Simulation-based verification of power aware System-on-Chip designs using UPF IEEE 1801