NDLI: FPGA implementation of two involutional block ciphers targeted to wireless sensor networks

Content Provider	IEEE Xplore Digital Library
Author	Xueying Zhang Heys, H.M. Cheng Li
Copyright Year	2011
Description	Author affiliation: Electrical and Computer Engineering, Memorial University, St. John's, NL, A1B 3X5, Canada (Xueying Zhang; Heys, H.M.; Cheng Li)
Abstract	In this paper, we investigate the energy cost of the FPGA implementation of two cryptographic algorithms targeted to wireless sensor networks (WSNs). Recent trends have seen the emergence of WSNs using sensor nodes based on reconfigurable hardware, such as a field-programmable gate arrays (FPGAs), thereby providing flexible functionality with higher performance than classical microcontroller based sensor nodes. In our study, we investigate the hardware implementation of involutional block ciphers since the characteristics of involution enables performing encryption and decryption using the same circuit. This characteristic is particularly appropriate for a wireless sensor node which requires the function of both encryption and decryption. Further, in order to consider the suitability of a cipher for application to a wireless sensor node, which is an energy constrained device, it is most critical to consider the cost of encryption in terms of energy consumption. Hence, we choose two involutional block ciphers, KHAZAD and BSPN, and analyze their energy efficiency for FPGA implementation.
Starting Page	232
Ending Page	236
File Size	265733
Page Count	5
File Format	PDF
ISBN	9781457701009
e-ISBN	9781457701016
DOI	10.1109/ChinaCom.2011.6158154
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2011-08-17
Publisher Place	China
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Wireless sensor networks security wireless sensor networks field programmable gate arrays Hardware Software Energy efficiency Table lookup Encryption Field programmable gate arrays block ciphers
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

FPGA Implementation and Energy Cost Analysis of Two Light-Weight Involutional Block Ciphers Targeted to Wireless Sensor Networks

An FPGA-based performance comparison of the 64-bit block ciphers

SIMON Says: Break Area Records of Block Ciphers on FPGAs

On a High-Performance and Balanced Method of Hardware Implementation for AES

Compact CLEFIA Implementation on FPGAS

Rapid prototyping of AES encryption for wireless communication system on FPGA

Efficient FPGA implementation of block cipher MISTY1

VLSI implementation of advance encryption algorithm using index technique

Hardware Implementation of Quasigroup Encryption for SCADA Networks

FPGA implementation of two involutional block ciphers targeted to wireless sensor networks

Similar Documents

FPGA Implementation and Energy Cost Analysis of Two Light-Weight Involutional Block Ciphers Targeted to Wireless Sensor Networks

An FPGA-based performance comparison of the 64-bit block ciphers

SIMON Says: Break Area Records of Block Ciphers on FPGAs

On a High-Performance and Balanced Method of Hardware Implementation for AES

Compact CLEFIA Implementation on FPGAS

Rapid prototyping of AES encryption for wireless communication system on FPGA

Efficient FPGA implementation of block cipher MISTY1

VLSI implementation of advance encryption algorithm using index technique

Hardware Implementation of Quasigroup Encryption for SCADA Networks

FPGA implementation of two involutional block ciphers targeted to wireless sensor networks