NDLI: A Hazard-Free Majority Voter for TMR-Based Fault Tolerance in Asynchronous Circuits

Content Provider	IEEE Xplore Digital Library
Author	Almukhaizim, S. Sinanoglu, O.
Copyright Year	2007
Description	Author affiliation: Kuwait Univ., Kuwait City (Almukhaizim, S.; Sinanoglu, O.)
Abstract	Triple-modular redundancy (TMR) is the simplest and most effective fault tolerant design method for ICs, where three copies of a given circuit are employed and a majority voter produces the voted output. Asynchronous circuits, however, exhibit various characteristics that limit the applicability of TMR on such designs. Specifically, the difficulty stems from the fact that asynchronous circuits communicate with their environment through hazard-free output transitions. This hazard-free property needs to be preserved when hardware providing fault tolerance is added. Therefore, performing TMR-based fault tolerance in asynchronous circuits requires the development of a hazard-free majority voter. In this work, we first demonstrate how and why a typical majority voter design would fail to preserve the hazard-free property of its response when a transient error occurs at one of its inputs. We then propose a novel hazard-free majority voter design for the TMR-based fault tolerant method. Finally, using PSpice simulations, we verify the effectiveness of the proposed voter design in preserving the hazard-free property of the response of an asynchronous circuit, and we assess its area overhead over that of a typical majority voter.
Starting Page	93
Ending Page	98
File Size	1831528
Page Count	6
File Format	PDF
ISBN	9781424418244
DOI	10.1109/IDT.2007.4437437
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2007-12-16
Publisher Place	Egypt
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Fault tolerance Logic circuits Design methodology Redundancy CMOS technology Hardware Hazards Protection Asynchronous circuits Clocks
Content Type	Text
Resource Type	Article

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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