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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Yu-Lung Lo Pei-Yuan Chou Hsiang-Hui Cheng Shu-Fen Tsai Wei-Bin Yang |
| Copyright Year | 2011 |
| Description | Author affiliation: Department of Electronic Engineering, National Kaohsiung Normal University, Kaohsiung, Taiwan, R.O.C. (Yu-Lung Lo; Pei-Yuan Chou; Hsiang-Hui Cheng) || Department of Microelectronics Engineering, National Kaohsiung Marine University, Kaohsiung, Taiwan, R.O.C. (Shu-Fen Tsai) || Department of Electrical Engineering Tamkang University Tamsui, Taipei, Taiwan, R.O.C. (Wei-Bin Yang) |
| Abstract | This paper describes a low power and low area multiphase digital DLL. The architecture of the proposed DLL uses coarse tune loop and fine tune loop to reduce the static phase error and accomplish faster locking time. The DLL was designed using a 0.35 μm standard CMOS process with a 3.3V supply voltage. Simulation results show that the proposed DLL can generate four-phase clock signals ranging from 320 MHz to 500 MHz within a single cycle. At 500 MHz, the peak-to-peak jitter is 6 ps and the total power consumption is 28.3 mW. Moreover, the proposed DLL's locking time is less than 24 clock cycles and the core area is 0.17 $mm^{2}.$ |
| Starting Page | 388 |
| Ending Page | 391 |
| File Size | 1034811 |
| Page Count | 4 |
| File Format | |
| ISBN | 9781612848631 |
| e-ISBN | 9781612848655 |
| DOI | 10.1109/ISICir.2011.6131978 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2011-12-12 |
| Publisher Place | Singapore |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Digital DLL Multiphase Detectors Delay lines Jitter Dual-Loop Control Solid state circuits Decoding Delay Clocks |
| Content Type | Text |
| Resource Type | Article |
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