NDLI: Low power methodology for an ASIC design flow based on high-level synthesis

Content Provider	IEEE Xplore Digital Library
Author	Bin Muslim, F. Qamar, A. Lavagno, L.
Copyright Year	2015
Description	Author affiliation: Dept. of Electron. & Telecommun., Politec. di Torino, Turin, Italy (Bin Muslim, F.; Qamar, A.; Lavagno, L.)
Abstract	Power management in system-on-chip (SoC) design has become very important in modern nanometric technologies. It is desirable to consider power optimization at the system-level for maximum power savings due to its higher level of abstraction. Clock gating and power gating are two well-known techniques for dynamic and leakage power reduction respectively. They can even be integrated to get maximum power reduction by using the same signal to control both. This work presents a methodology using both these techniques to save power of an inverse discrete cosine transform (IDCT) design when the register transfer level (RTL) is generated automatically by high-level synthesis (HLS). Power gating is implemented by capturing the power intent using common power format (CPF). This work mainly highlights the prospects of integrating CPF with automatically generated RTL using HLS flow. Saving in dynamic power by a factor of around 10× is obtained through clock gating while more than 50% saving in static power is obtained through power gating. Power gating also results in some area overhead.
Starting Page	11
Ending Page	15
File Size	214825
Page Count	5
File Format	PDF
ISBN	9789532900569
DOI	10.1109/SOFTCOM.2015.7314103
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2015-09-16
Publisher Place	Croatia
Access Restriction	Subscribed
Rights Holder	University of Split, FESB
Subject Keyword	Power demand High-Level Synthesis Clock gating SoC Switches Low power Power gating Optimization Standards Logic gates Hardware Common Power Format Clocks
Content Type	Text
Resource Type	Article

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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