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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Dyi-Chung Hu Tsung Jen Yang Ferry Hu |
| Copyright Year | 2008 |
| Description | Author affiliation: Technol. Center, ACE Technol., Inc., Hinchu (Dyi-Chung Hu; Tsung Jen Yang; Ferry Hu) |
| Abstract | SiP technology has been one of the alternative solutions to system integration. Compare to SoC, SiP has the advantages of integration of dies made from different technologies, e.g. GaAs and Silicon. In some cases, SiP technology may provide faster time to the market and at a lower cost. Despite many research activities, there are few companies actually went into mass production using SiP embedded technology due to lack of standard process and equipment. ACET has developed a SiP embedded structure and process for mass production. Current, ACET has mass production packages using 6" and 8" panel format. In order to further enhance the productivity and efficiency of the SiP embedded technology, going into a larger substrate is a next logical step. In the paper, we shall describe the development of SiP embedded technology in ACET. We also demonstrated successfully of building packages using 12 inch format in our manual line. |
| Starting Page | 387 |
| Ending Page | 389 |
| File Size | 2710569 |
| Page Count | 3 |
| File Format | |
| ISBN | 9781424436231 |
| DOI | 10.1109/IMPACT.2008.4783893 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2008-10-22 |
| Publisher Place | Taiwan |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Wafer bonding Mass production Surface reconstruction Costs Metallization Gallium arsenide Silicon Wafer scale integration Substrates Electronics packaging |
| Content Type | Text |
| Resource Type | Article |
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