NDLI: Effect of Process and Layout on Strain Enhancement from Dual Stress Liners

Content Provider	IEEE Xplore Digital Library
Author	Moroz, V. Munkang Choi Xi Wie Lin Pramanik, D.
Copyright Year	2007
Abstract	Tensile and compressive stressed nitride liners have been used to increase the carrier mobility in n-channel and p-channel silicon transistors respectively. Simulations indicate how much of the stress in the film is transferred to the channel region and the magnitude of the stress in different directions. A simple bulk piezoresistive model was used to estimate the effect on carrier mobility. It is shown in the case of the n-channel transistors that the enhancement is due to the vertical stress component whereas in the case of p-channel devices the enhancement is due to the in-plane stresses. The effect of different process conditions such as film stress, thickness and method of deposition, on mobility enhancement, was also characterized. It is shown that the enhancement saturates with increasing nitride thickness but scales proportionally with the film stress. Detailed studies of the effect of the circuit layout on the final channel stress allow the critical layout parameters to be identified. The variation of device performance with the layout parameters is quantified and can be used to define design rules as well as equations to modify the device characteristics based on layout.
Starting Page	63
Ending Page	63
File Size	34604
Page Count	1
File Format	PDF
ISBN	1424402670
ISSN	07496877
DOI	10.1109/UGIM.2006.4286354
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2006-06-25
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Capacitive sensors Tensile stress Compressive stress Tensile strain Silicon Piezoresistance Circuits Equations
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

Mobility and Strain Effects on <110>/(110) SiGe channel pMOSFETs for High Current Enhancement

Performance Enhancement of pMOSFETs Depending on Strain, Channel Direction, and Material

Comparison of Uniaxial Wafer Bending and Contact-Etch-Stop-Liner Stress Induced Performance Enhancement on Double-Gate FinFETs

Impact of width effect on performance enhancement in NMOSFETs with silicon-carbon alloy stressor and stress CESL

Uniaxial strain effects on silicon nanowire pMOSFET and single-hole transistor at room temperature

Variations of hole mass in p-MOSFETs under process-induced mechanical stress

Piezomobility description of strain-induced mobility

Experimental study of biaxial and uniaxial strain effects on carrier mobility in bulk and ultrathin-body SOI MOSFETs

Strain Effects of Si and SiGe Channel on (100) and (110) Si Surfaces for Advanced CMOS Applications

Effect of Process and Layout on Strain Enhancement from Dual Stress Liners

Similar Documents

Mobility and Strain Effects on <110>/(110) SiGe channel pMOSFETs for High Current Enhancement

Performance Enhancement of pMOSFETs Depending on Strain, Channel Direction, and Material

Comparison of Uniaxial Wafer Bending and Contact-Etch-Stop-Liner Stress Induced Performance Enhancement on Double-Gate FinFETs

Impact of width effect on performance enhancement in NMOSFETs with silicon-carbon alloy stressor and stress CESL

Uniaxial strain effects on silicon nanowire pMOSFET and single-hole transistor at room temperature

Variations of hole mass in p-MOSFETs under process-induced mechanical stress

Piezomobility description of strain-induced mobility

Experimental study of biaxial and uniaxial strain effects on carrier mobility in bulk and ultrathin-body SOI MOSFETs

Strain Effects of Si and SiGe Channel on (100) and (110) Si Surfaces for Advanced CMOS Applications

Effect of Process and Layout on Strain Enhancement from Dual Stress Liners