NDLI: A 2.4-GHz, Wide Tuning Range GmC VCO Using a Novel Load Biasing Technique

Content Provider	IEEE Xplore Digital Library
Author	Verma, V. Papalias, T.
Copyright Year	2007
Description	Author affiliation: San Jose State Univ., San Jose (Verma, V.)
Abstract	This paper presents a 2.4-GHz monolithic GmC fully differential voltage controlled oscillator (VCO) fabricated in 0.24-mum CMOS technology with a wide tuning range between 1.77 GHz and 2.73 GHz. This VCO can be used for data clock recovery applications in optical receivers for such standards as SONET OC-48 or European SDH STM-16. Two published techniques for quadrature generation are discussed for use in data clock recovery. The circuit implementation is purely transistor based OTA stages with the entire VCO covering 60 mum x 90 mum. A novel technique for active load biasing is introduced which provides marginal temperature insensitivity and eliminates a need for external bias source. The power dissipation is less than 50 mW at 2.0 V power supply and the measured phase-noise is -93 dBc/Hz at 2 MHz offset.
Starting Page	201
Ending Page	206
File Size	2308594
Page Count	6
File Format	PDF
ISBN	1424402670
ISSN	07496877
DOI	10.1109/UGIM.2006.4286382
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2006-06-25
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Voltage-controlled oscillators Optical tuning CMOS technology Clocks Circuit optimization Optical receivers SONET Synchronous digital hierarchy Temperature Power dissipation ring oscillator CMOSFET oscillator SONET OC-48 wide tuning range GmC oscillator
Content Type	Text
Resource Type	Article

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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