NDLI: High resolution CD-SEM system

Please wait, while we are loading the content...

2014 IEEE 23rd Asian Test Symposium

2013 22nd Asian Test Symposium

2012 IEEE 21st Asian Test Symposium

2011 Asian Test Symposium

2010 19th IEEE Asian Test Symposium

2009 Asian Test Symposium

2008 17th Asian Test Symposium

16th Asian Test Symposium (ATS 2007)

2006 15th Asian Test Symposium

14th Asian Test Symposium (ATS'05)

13th Asian Test Symposium

2003 Test Symposium

Proceedings of the 11th Asian Test Symposium, 2002. (ATS '02).

Proceedings 10th Asian Test Symposium

Proceedings of the Ninth Asian Test Symposium

Proceedings Eighth Asian Test Symposium (ATS'99)

A method of test generation for weakly testable data paths using test knowledge extracted from RTL description

Automatic test pattern generation for improving the fault coverage of microprocessors

On compact test sets for multiple stuck-at faults for large circuits

Identification of feedback bridging faults with oscillation

Defining SRAM resistive defects and their simulation stimuli

Vector-based functional fault models for delay faults

Easily path delay fault testable non-restoring cellular array dividers

March tests for word-oriented two-port memories

An evaluation of test generation algorithms for combinational circuits

Research and implementation of a high speed test generation for ultra large scale combinational circuits

Pattern sensitivity: a property to guide test generation for combinational circuits

An accurate logic threshold voltages determination model for CMOS gates to facilitate test generation and fault simulation

Circuit partitioning for low power BIST design with minimized peak power consumption

A BIST TPG approach for interconnect testing with the IEEE 1149.1 STD

Test scheduling with loop folding and its application to test configurations with accumulators

A polynomial-time algorithm for power constrained testing of core based systems

Accelerating test data processing

Procedure to overcome the Byzantine General's problem for bridging faults in CMOS circuits

A novel fault-detection technique for the parallel multipliers and dividers

A fault partitioning method in parallel test generation for large scale VLSI circuits

Fault simulation techniques to reduce IDDQ measurement vectors for sequential circuits

On an effective selection of IDDQ measurement vectors for sequential circuits

Scan chain diagnosis using IDDQ current measurement

I/sub DDQ/ current dependency on test vectors and bridging resistance

A parallel generation system of compact IDDQ test sets for large combinational circuits

An effective methodology for mixed scan and reset design based on test generation and structure of sequential circuits

Genetic algorithm based test generation for sequential circuits

Fault (in)dependent cost estimates and conflict-directed backtracking to guide sequential circuit test generation

Static and dynamic test sequence compaction methods for acyclic sequential circuits using a time expansion model

Activation function manipulation for fault tolerant feedforward neural networks

Fault-tolerant analysis of feedback neural networks with threshold neurons

Fault-tolerant strategies and their design methods for application software

Test by distributed monitoring

Optimized statistical analog fault simulation

Analog metrology and stimulus selection in a noisy environment

Efficient test set design for analog and mixed-signal circuits and systems

Railway signaling safety-critical software testing based on dynamic decision table

A novel testing approach for safety-critical software

How to design an environment simulator for safety critical software testing

New DFT techniques of non-scan sequential circuits with complete fault efficiency

Identification of redundant crosspoint faults in sequential PLAs with fault-free hardware reset

An embedded core DFT scheme to obtain highly compressed test sets

Scenario based integration testing for object-oriented software development

An approach to testing the nonexistence of initial state in Z specifications

Generating test cases for real-time software by time Petri nets model

Defect level prediction using multi-model fault coverage

A high-level synthesis approach to partial scan design based on acyclic structure

An input control technique for power reduction in scan circuits during test application

A simplified method for testing the IBM pipeline partial-scan microprocessor

A new algorithm for retiming-based partial scan

Intelligent EB test system for automatic VLSI fault tracing

Multiple fault diagnosis in logic circuits using EB tester and multiple/single fault simulators

Practical application of automated fault diagnosis for stuck-at, bridging, and measurement condition dependent faults in fully scanned sequential circuits

Minimizing the number of programming steps for diagnosis of interconnect faults in FPGAs

Minimizing the number of test configurations for different FPGA families

Testing the logic cells and interconnect resources for FPGAs

I/sub DDQ/ testing of input/output resources of SRAM-based FPGAs

High resolution CD-SEM system

Investigation of Ga contamination due to analysis by dual beam FIB

Failure analysis case studies using the IR-OBIRCH (infrared optical beam induced resistance change) method

Proceedings Seventh Asian Test Symposium (ATS'98) (Cat. No.98TB100259)

Proceedings Sixth Asian Test Symposium (ATS'97)

Proceedings of the Fifth Asian Test Symposium (ATS'96)

Proceedings of the Fourth Asian Test Symposium

Proceedings of IEEE 3rd Asian Test Symposium (ATS)

Proceedings of 1993 IEEE 2nd Asian Test Symposium (ATS)

Proceedings First Asian Test Symposium (ATS `92)

High resolution CD-SEM system

Content Provider	IEEE Xplore Digital Library
Author	Ose, Y. Ezumi, M. Todokoro, H.
Copyright Year	1999
Description	Author affiliation: Hitachi Ltd., Ibaraki, Japan (Ose, Y.)
Abstract	Because of rapidly decreasing line-width of integrated circuits, it is necessary to measure and control their critical dimensions with high accuracy. We have developed a new critical-dimension-measurement scanning electron microscope (CD-SEM) S-9000 series, which has a new electron optics with retarding and boosting electric fields. To optimize the boosting voltage we have developed optics simulators that are capable of computing aberration coefficients and secondary electron detection efficieny in electric and magnetic mixed fields. At the optimized boosting voltage of around 5 kV for a final accelerating voltage of 800 V, not only 3 nm resolution but also highlighted bottom imaging of high aspect ratio contact holes is obtained.
Starting Page	383
Ending Page	388
File Size	267781
Page Count	6
File Format	PDF
ISBN	0769503152
ISSN	10817735
DOI	10.1109/ATS.1999.810779
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1999-11-18
Publisher Place	China
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Boosting Voltage Electron optics Magnetic field measurement Integrated circuit measurements Optical microscopy Scanning electron microscopy Computational modeling Circuit simulation Optical computing
Content Type	Text
Resource Type	Article
Subject	Electrical and Electronic Engineering

Central Library (ISO-9001:2015 Certified)
Indian Institute of Technology Kharagpur
Kharagpur, West Bengal, India | PIN - 721302

See location in the Map
03222 282435
Mail: support@ndl.gov.in

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in