NDLI: Research and implementation of a high speed test generation for ultra large scale combinational circuits

Content Provider	IEEE Xplore Digital Library
Author	Zhide Zeng Jihua Chen Hefeng Cao
Copyright Year	1999
Description	Author affiliation: Dept. of Comput. Sci., Nat. Univ. of Defense Technol., Hunan, China (Zhide Zeng)
Abstract	In this paper a high-speed test generation method for ultra large scale combinational circuits and full-scan circuits is presented. This method adopts the finite backtracking test pattern generation method to generate test pattern, and uses the parallel-pattern single-fault propagating method with n (machine word length) test vectors to validate the fault coverage. The test generation and fault simulation are integrated with n to 1 tightly coupled mode. The method obtains desired results: shorter test pattern length, higher fault coverage and efficiency from execution of 10 ISCAS-85 benchmark circuits.
Starting Page	70
Ending Page	74
File Size	49221
Page Count	5
File Format	PDF
ISBN	0769503152
ISSN	10817735
DOI	10.1109/ATS.1999.810731
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1999-11-18
Publisher Place	China
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Large-scale systems Circuit testing Circuit faults Circuit simulation Combinational circuits Test pattern generators Computer science AC generators Read only memory Life estimation
Content Type	Text
Resource Type	Article
Subject	Electrical and Electronic Engineering

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Research and implementation of a high speed test generation for ultra large scale combinational circuits