NDLI: Automatic test pattern generation for improving the fault coverage of microprocessors

Content Provider	IEEE Xplore Digital Library
Author	Hirase, J. Yoshimura, S. Sezaki, T.
Copyright Year	1999
Description	Author affiliation: Matsushita Commun. Ind. Co. Ltd., Japan (Hirase, J.)
Abstract	In order to improve the quality of microprocessor tests, the use of instruction sets for testing is indispensable. In this paper, we will present a new method consisting of the automatic generation of a functional test pattern, formed by a combination of instructions sets and enabling the efficient improvement of the fault coverage. With this method, a test pattern is first generated to test all of an S number of instruction mnemonics. Then, for the faults that were undetected by that test pattern, an L number of sets of K number of instructions are drawn from the S number of instructions, and the set enabling the efficient improvement of the fault coverage is selected. By repeating this procedure, a high fault coverage can be obtained with a short test pattern. The effectiveness of our method was proved by the results of experiments obtained with the software that was created based on this method.
Starting Page	13
Ending Page	19
File Size	299722
Page Count	7
File Format	PDF
ISBN	0769503152
ISSN	10817735
DOI	10.1109/ATS.1999.810723
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1999-11-18
Publisher Place	China
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Automatic test pattern generation Microprocessors Logic testing System testing Automatic testing Software testing Circuit testing Circuit faults Design for testability Read only memory
Content Type	Text
Resource Type	Article
Subject	Electrical and Electronic Engineering

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

High-coverage ATPG for datapath circuits with unimplemented blocks

Functional testing of microprocessors with graded fault coverage

Automatic generation and validation of memory test models for high performance microprocessors

Test strategies for a family of complex MCMs

On a logical fault model H1SGLF for enhancing defect coverage

Automatic Functional Test Generation - A Reality

Design for sequential testability: an internal state reseeding approach for 100 % fault coverage

Special ATPG to correlate test patterns for low-overhead mixed-mode BIST

Satisfiability-Based Automatic Test Program Generation and Design for Testability for Microprocessors

Automatic test pattern generation for improving the fault coverage of microprocessors

Similar Documents

High-coverage ATPG for datapath circuits with unimplemented blocks

Functional testing of microprocessors with graded fault coverage

Automatic generation and validation of memory test models for high performance microprocessors

Test strategies for a family of complex MCMs

On a logical fault model H1SGLF for enhancing defect coverage

Automatic Functional Test Generation - A Reality

Design for sequential testability: an internal state reseeding approach for 100 % fault coverage

Special ATPG to correlate test patterns for low-overhead mixed-mode BIST

Satisfiability-Based Automatic Test Program Generation and Design for Testability for Microprocessors

Automatic test pattern generation for improving the fault coverage of microprocessors