NDLI: A method of generating tests for marginal delays and delay faults in combinational circuits

Content Provider	IEEE Xplore Digital Library
Author	Takahashi, H. Matsunaga, T. Boateng, K.O. Takamatsu, Y.
Copyright Year	1997
Description	Author affiliation: Dept. of Comput. Sci., Ehime Univ., Matsuyama, Japan (Takahashi, H.)
Abstract	In this paper, we propose an algorithmic method for generating a test for marginal delays and gate delay faults, called an MD test. The time at which the MD test activates the latest transition at the primary output changes linearly with the size of the target delay. (1) The MD tests determine at a given clock rate (observation time) whether a circuit tender test is marginal chip or not. (2) The MD tests determine the maximum circuit clock speeds. (3) The MD test detects the target gate delay fault regardless of the size of the fault by comparing the latest transition time at the primary output of the fault-free circuit and that of the faulty circuit. In order to determine the detectable size of gate delay faults the proposed method introduces a new extended timed calculus which calculates both the latest transition time at the line in the fault-free circuit and the transition time at the same line affected by a gate delay fault of maximum fault size. We also demonstrate experimental results for gate delay faults on ISCAS benchmark circuits to show the performance of our method.
Starting Page	320
Ending Page	325
File Size	660769
Page Count	6
File Format	PDF
ISBN	0818682094
ISSN	10817735
DOI	10.1109/ATS.1997.643977
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1997-11-17
Publisher Place	Japan
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Circuit testing Circuit faults Combinational circuits Delay effects Clocks Robustness Electrical fault detection Fault detection Computer science Calculus
Content Type	Text
Resource Type	Article
Subject	Electrical and Electronic Engineering

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