NDLI: Memory efficient ATPG for path delay faults

Content Provider	IEEE Xplore Digital Library
Author	Wangning Long Zhongchen Li Shiyuan Yang Yinghua Min
Copyright Year	1997
Description	Author affiliation: Dept. of Autom., Tsinghua Univ., Beijing, China (Wangning Long)
Abstract	A memory efficient test pattern generator for path delay faults, DTPG, is presented in this paper, which uses the efficient path identifier to represent a path. A compact bit table, path information table, is proposed to store test information efficiently. Furthermore, DTPG is capable of identifying functional sensitizable paths, which account for large percent of paths in many circuits. The experimental results show that DTPG is memory efficient. It generates tests for C3540 with 57 million paths and preserves the testability information for all paths. Experimental results show the influence of stepwise mandatory sensitization, multiple backtrace, and backtracking limits on the cpu time consumed by delay test generation process.
Starting Page	326
Ending Page	331
File Size	654694
Page Count	6
File Format	PDF
ISBN	0818682094
ISSN	10817735
DOI	10.1109/ATS.1997.643978
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1997-11-17
Publisher Place	Japan
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Automatic test pattern generation Circuit testing Circuit faults Test pattern generators System testing Delay effects Delay systems Robustness Fault diagnosis Logic testing
Content Type	Text
Resource Type	Article
Subject	Electrical and Electronic Engineering

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