NDLI: Fast functional testing of delay-insensitive circuits

Content Provider	IEEE Xplore Digital Library
Author	Pagey, S.
Copyright Year	1995
Description	Author affiliation: Cadence Design Syst. Ltd., Noida, India (Pagey, S.)
Abstract	Although the advantages of delay-insensitive and self-timed circuits with respect to speed and operation are known, their advantages in terms of testing are not examined. We focus our attention on testing four-phase handshake signalling based circuits designed using Martin's method. Due to the distributed nature of the control part of a delay-insensitive circuit, it is possible to simultaneously test many non-interfering portions of the circuit, thereby substantially reducing the testing time. In order to ensure that the circuit performs in a delay-insensitive manner even during testing, certain OR gates in the synthesized circuit required to be replaced by OR/C blocks. An OR/C block operates as an OR gate during normal operation and as a C-element during testing. Identification of the OR gates to be replaced by OR/C blocks and the generation of test sequences is performed by analyzing the program flow graph of the given circuit.
Starting Page	375
Ending Page	381
File Size	673689
Page Count	7
File Format	PDF
ISBN	0818671297
DOI	10.1109/ATS.1995.485363
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1995-11-23
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Circuit testing Delay Circuit faults Flow graphs Circuit synthesis Asynchronous circuits Electrical fault detection Fault detection Protocols Automatic testing
Content Type	Text
Resource Type	Article

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