NDLI: Serial transistor network modeling for bridging fault simulation

Content Provider	IEEE Xplore Digital Library
Author	Renovell, M. Huc, P. Bertrand, Y.
Copyright Year	1995
Description	Author affiliation: Lab. d'Inf., Robotique et Microelectron., Univ. des Sci. et Tech. du Languedoc, Montpellier, France (Renovell, M.; Huc, P.; Bertrand, Y.)
Abstract	The most recent bridging fault models, the voting and the biased voting model use the concept of relative transistor strength during fault simulation. A SPICE pre-simulation allows one to determine the relative strength of unit dimension transistors; the results stored in tables are then used during fault simulation. This concept is very efficient for single transistor and parallel transistor networks but suffers when serial transistor networks are considered. The relative strength of serial transistor networks implies the use of many tables (for 2, 3, 4, ... serial n and p transistors) slowing down the fault simulation procedure. This paper presents a new model for serial transistor networks which accelerates bridging fault simulation. This model allows one to easily define a single transistor equivalent to the serial network. In this way, any bridging fault involving any transistor network can be considered as a bridging fault involving single transistors. This model used with either the voting or the biased voting model decreases the number of required tables increasing the efficiency of the bridging fault simulation.
Starting Page	100
Ending Page	106
File Size	557908
Page Count	7
File Format	PDF
ISBN	0818671297
DOI	10.1109/ATS.1995.485323
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1995-11-23
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Circuit faults Voting Semiconductor device modeling Testing SPICE Logic circuits Threshold voltage Robots Acceleration CMOS process
Content Type	Text
Resource Type	Article

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