NDLI: A STAFAN-like functional testability measure for register-level circuits

Content Provider	IEEE Xplore Digital Library
Author	Ravikumar, C.P. Saund, G.S. Agrawal, N.
Copyright Year	1995
Description	Author affiliation: Dept. of Electr. Eng., Indian Inst. of Technol., Delhi, India (Ravikumar, C.P.)
Abstract	STAFAN (statistical fault analysis) is a well known testability analysis program which predicts the fault coverage of a digital circuit under the stuck-at fault model, without actually performing fault simulation. STAFAN offers speed advantage over other testability analysis programs such as SCOAP; further, it explicitly predicts the fault coverage for a given test set, unlike other testability measures which are harder to interpret. STAFAN works on gate-level digital circuits composed of basic logic gates. In this work, we show how a STAFAN-like testability analysis program can be constructed for circuits built out of register-level modules. With the proliferation of high-level synthesis and testability-driven synthesis, it is becoming more and more important to have fast testability analysis tools which operate on register-level components such as adders, multipliers, multiplexers, busses, and so on. Our testability analysis algorithm, which we call F-STAFAN, fills this void. We have implemented F-STAFAN on a Sun/SPARC workstation and describe its performance on several register-level circuits.
Starting Page	192
Ending Page	198
File Size	593837
Page Count	7
File Format	PDF
ISBN	0818671297
DOI	10.1109/ATS.1995.485336
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1995-11-23
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Circuit testing Circuit faults Performance analysis Digital circuits Predictive models Performance evaluation Analytical models Circuit simulation Velocity measurement Logic gates
Content Type	Text
Resource Type	Article

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