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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Storey, T. |
| Copyright Year | 2004 |
| Description | Author affiliation: BAE Syst., Manassas, VA, USA (Storey, T.) |
| Abstract | DSM manufacturing is expensive. It has been estimated that it costs in excess of /spl rlarr2/ to build a 90nm line. DSM designs are much more susceptible to topological based deformations. Finally, in the DSM environment, it becomes increasingly difficult to separate design vs. process marginalities. Clearly one goal of design for manufacturability is to avoid such sensitivities where identified. This requires an in depth knowledge of the process "sweet spots," acquired initially via test sites especially developed with this objective, followed by focussed diagnosis of the product itself. Since it is unrealistic to assume that ATE is an economically viable solution for the speed requirements, at-speed BIST techniques prevails. |
| Sponsorship | IEEE Comput. Soc. Test Technol. Tech. Council IEEE Philadelphia Sect |
| File Size | 83548 |
| File Format | |
| ISBN | 0780385802 |
| DOI | 10.1109/TEST.2004.1387430 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2004-10-26 |
| Publisher Place | USA |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Costs Semiconductor device manufacture Environmental economics System testing Vehicles Manufacturing Circuit testing Microprocessors Graphics Inspection |
| Content Type | Text |
| Resource Type | Article |
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