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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Schuttert, R. van Geest, D.C.L. |
| Copyright Year | 2004 |
| Description | Author affiliation: Philips Res., Eindhoven, Netherlands (Schuttert, R.; van Geest, D.C.L.) |
| Abstract | Analogue clusters on boards are traditionally tested in mass production using a Bed-of-Nails, often combined with functional system tests. In general this approach requires additional board area to create test access, is not very flexible and is hard to re-use. On-chip methods provide a solution to overcome these drawbacks and are already widely used in the form of boundary scan for digital interconnections. For analogue interconnections also on-chip solutions are available. We analysed the coverage and application of two on-chip methods, IEEE Std 1149.4 and the re-usage of existing design-for-testability for on-chip mixed-signal blocks. It was found that a reduction board test costs as well as test development time can be achieved by using, or rather reusing on-chip alternatives. |
| Sponsorship | IEEE Comput. Soc. Test Technol. Tech. Council IEEE Philadelphia Sect |
| Starting Page | 375 |
| Ending Page | 383 |
| File Size | 820272 |
| Page Count | 9 |
| File Format | |
| ISBN | 0780385802 |
| DOI | 10.1109/TEST.2004.1386973 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2004-10-26 |
| Publisher Place | USA |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | System testing Circuit testing Analog integrated circuits Costs Consumer products Pins Integrated circuit testing Signal analysis Integrated circuit interconnections Analog-digital conversion |
| Content Type | Text |
| Resource Type | Article |
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