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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Syal, M. Chakravarty, S. Hsiao, M.S. |
| Copyright Year | 2004 |
| Description | Author affiliation: Bradley Dept. of Electr. & Comput. Eng., Virginia Tech., Blacksburg, VA, USA (Syal, M.) |
| Abstract | This work presents a novel technique to identify functionally untestable transition faults in latch based designs with multiple clock domains, bringing to light unaddressed issues related to untestable fault identification in such design environments. We also introduce and provide a solution to a new variant of un-testability analysis wherein "architectural constraints'' are absorbed during the analysis. We give our tool the capability of handling transition faults resulting from defects of varying sizes, and evaluate our tool for various industrial circuits. The proposed algorithm is compared with a state-of-the-art sequential ATPG tool, and our method has shown much better performance both in the context of scan ATPG and functional test development. Results indicate that the proposed technique identifies considerably more untestable transition faults than those that can be deduced from the knowledge of untestable stuck-at faults. Additional insights from our results point to a greater need to eliminate untestable transition faults as compared to stuck-at faults, for more efficient test pattern generation and accurate coverage computation. |
| Sponsorship | IEEE Comput. Soc. Test Technol. Tech. Council IEEE Philadelphia Sect |
| Starting Page | 1034 |
| Ending Page | 1043 |
| File Size | 800368 |
| Page Count | 10 |
| File Format | |
| ISBN | 0780385802 |
| DOI | 10.1109/TEST.2004.1387369 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2004-10-26 |
| Publisher Place | USA |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Fault diagnosis Clocks Circuit faults Delay Fault detection Latches Circuit testing Automatic test pattern generation Flip-flops Computer architecture |
| Content Type | Text |
| Resource Type | Article |
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