NDLI: Analysis of pattern-dependent and timing-dependent failures in an experimental test chip

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Analysis of pattern-dependent and timing-dependent failures in an experimental test chip

Content Provider	IEEE Xplore Digital Library
Author	Chang, J.T.-Y. Chao-Wen Tseng Li, C.-M.J. Purtell, M. McCluskey, E.J.
Copyright Year	1998
Description	Author affiliation: Center for Reliable Comput., Stanford Univ., CA, USA (Chang, J.T.-Y.)
Abstract	This paper presents the results for very detailed studies of pattern and timing-dependent failures from the 309 dies in the retest of an experimental test chip. 22 out of the 50 CUTs with pattern-dependent failures had test escapes if the test sets were reordered. Some timing-dependent failures became timing-independent combinational (TIC) defects at very low voltage. Multiple-detect single stuck fault test sets have high transition fault coverage. Most dies with TIC or non-TIC defects were close to gross failures or next to the wafer periphery.
Starting Page	184
Ending Page	193
File Size	987752
Page Count	10
File Format	PDF
ISBN	0780350936
ISSN	10893539
DOI	10.1109/TEST.1998.743151
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1998-10-18
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Failure analysis Pattern analysis Probes Circuit testing Voltage System testing Packaging Very large scale integration Clocks Circuit faults
Content Type	Text
Resource Type	Article
Subject	Applied Mathematics Electrical and Electronic Engineering

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