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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Han Bin Kim Takahashi, T. Dong Sam Ha |
| Copyright Year | 1998 |
| Description | Author affiliation: Bradley Dept. of Electr. & Comput. Eng., Virginia Polytech. Inst. & State Univ., Blacksburg, VA, USA (Han Bin Kim) |
| Abstract | Existing high-level BIST synthesis methods focus on one objective, minimizing either area overhead or test time. Hence, those methods do not render exploration of large design space, which may result in a local optimum. In this paper, we present a method which aims to address the problem. Our method tries to find an optimal register assignment for each k-test session. Therefore, it offers a range of designs to the designer with different figures of merit in area and test time. Experimental results show that our method performs better than or comparable to existing BIST synthesis systems. |
| Starting Page | 154 |
| Ending Page | 163 |
| File Size | 1116050 |
| Page Count | 10 |
| File Format | |
| ISBN | 0780350936 |
| ISSN | 10893539 |
| DOI | 10.1109/TEST.1998.743148 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 1998-10-18 |
| Publisher Place | USA |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Automatic testing Built-in self-test Circuit testing Circuit synthesis Control system synthesis System testing Process design Logic design Hardware Circuit faults |
| Content Type | Text |
| Resource Type | Article |
| Subject | Applied Mathematics Electrical and Electronic Engineering |
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