NDLI: Why would an ASIC foundry accept anything less than full scan?

Content Provider	IEEE Xplore Digital Library
Author	Oakland, S.F.
Copyright Year	1997
Description	Author affiliation: Microelectron. Div., IBM Corp., Essex Junction, VT, USA (Oakland, S.F.)
Abstract	A key force behind IBM's growth in the application-specific integrated circuit (ASIC) market is the ability to sign off on multi-million-gate designs without requiring test vectors, presenting a savings in both time and money to customers. Once a customer ensures (via formal verification and/or functional simulation) that the design functions as required, static tinting analysis (STA) ensures that the design achieves the required performance targets. Extensive model-to-hardware correlation assures correctness of the timing analysis models, enabling IBM to assure that the design can be manufactured to the required performance targets. Through a combination of full-scan and boundary-scan design-for-test (DFT) structures, the IBM ASIC methodology ensures that automatically generated test patterns will run correctly on test equipment; typically achieving 99+% stuck-fault coverage. In the case of a repeatable manufacturing defect, full-scan-based diagnostic software isolates the problem without customer involvement.
File Size	119119
File Format	PDF
ISBN	0780342097
ISSN	10893539
DOI	10.1109/TEST.1997.639721
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1997-11-06
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Application specific integrated circuits Foundries Circuit testing Performance analysis Design for testability Integrated circuit testing Formal verification Analytical models Circuit simulation Timing
Content Type	Text
Resource Type	Article
Subject	Applied Mathematics Electrical and Electronic Engineering

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

Automatic characterization and modeling (ASIC design)

Design for testability using behavioral models

A Data Path Synthesis Method to Self-Testable Application Specific Integrated Circuit (ASIC)

Tutorial on design for testability (DFT) "An ASIC design philosophy for testability from chips to systems"

Design automation: pre-layout design verification and design submission for BiCMOS ASIC arrays

Robust scan-based logic test in VDSM technologies

Application of boundary-scan and full-chip BIST to a 3 ASIC chip set

CrossCheck: an ASIC testability solution

BIST Techniques for ASIC Design

Why would an ASIC foundry accept anything less than full scan?

Similar Documents

Automatic characterization and modeling (ASIC design)

Design for testability using behavioral models

A Data Path Synthesis Method to Self-Testable Application Specific Integrated Circuit (ASIC)

Tutorial on design for testability (DFT) "An ASIC design philosophy for testability from chips to systems"

Design automation: pre-layout design verification and design submission for BiCMOS ASIC arrays

Robust scan-based logic test in VDSM technologies

Application of boundary-scan and full-chip BIST to a 3 ASIC chip set

CrossCheck: an ASIC testability solution

BIST Techniques for ASIC Design

Why would an ASIC foundry accept anything less than full scan?