NDLI: Testability analysis and ATPG on behavioral RT-level VHDL

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Testability analysis and ATPG on behavioral RT-level VHDL

Content Provider	IEEE Xplore Digital Library
Author	Corno, F. Prinetto, P. Sonza Reorda, M.
Copyright Year	1997
Description	Author affiliation: Dipt. di Autom. e Inf., Politecnico di Torino, Italy (Corno, F.)
Abstract	This paper proposes an environment to address testability analysis and test pattern generation on VHDL descriptions at the RT-level. The proposed approach, based on a suitable fault model and an ATPG algorithm, is experimentally shown to provide a good estimate of the final gate-level fault coverage, and to give test patterns with excellent fault coverage properties. The approach, being based on an abstract representation, is particularly suited for large circuits, where gate-level ATPGs are often inefficient.
Starting Page	753
Ending Page	759
File Size	743090
Page Count	7
File Format	PDF
ISBN	0780342097
ISSN	10893539
DOI	10.1109/TEST.1997.639688
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1997-11-06
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Automatic test pattern generation Circuit faults Circuit testing Test pattern generators Circuit synthesis Algorithm design and analysis Hardware design languages Genetic algorithms Automatic testing Pattern analysis
Content Type	Text
Resource Type	Article
Subject	Applied Mathematics Electrical and Electronic Engineering

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