NDLI: Test width compression for built-in self testing

Content Provider	IEEE Xplore Digital Library
Author	Chakrabarty, K. Murray, B.T. Jian Liu Minyao Zhu
Copyright Year	1997
Description	Author affiliation: Dept. of Electr. Comput. Eng., Boston Univ., MA, USA (Chakrabarty, K.)
Abstract	We present a method for designing test generator circuits (TGCs) that incorporate a precomputed test set to in the patterns they produce. Our method uses width compression based on the property of d-compatibles, which allows us to encode to more efficiently than previous methods that use only compatibles and inverse compatibles. The TGC consists of a counter, which generates a set of encoded test patterns, and a decompression circuit consisting of simple binary decoders that generate a final sequence containing T/sub D/. These TGCs are applicable to embedded-core circuits whose detailed designs are not available. We demonstrate the effectiveness of our approach by presenting experimental results for the ISCAS 85 and ISCAS CAS 89 benchmark circuits.
Starting Page	328
Ending Page	337
File Size	1077641
Page Count	10
File Format	PDF
ISBN	0780342097
ISSN	10893539
DOI	10.1109/TEST.1997.639634
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1997-11-06
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Automatic testing Circuit testing Built-in self-test Circuit faults Logic testing Test pattern generators Costs Flip-flops Research and development Design methodology
Content Type	Text
Resource Type	Article
Subject	Applied Mathematics Electrical and Electronic Engineering

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

Design of built-in test generator circuits using width compression

Test-set embedding based on width compression for mixed-mode BIST

Test set embedding based on width compression for mixed-mode BIST

A methodology to design efficient BIST test pattern generators

Configuring flip-flops to BIST registers

Hierarchical Test Compression for SoC Designs

Low cost BIST for EDAC circuits

Pseudorandom testing for boundary-scan design with built-in self-test

Two-dimensional test data decompressor for multiple scan designs

Test width compression for built-in self testing

Similar Documents

Design of built-in test generator circuits using width compression

Test-set embedding based on width compression for mixed-mode BIST

Test set embedding based on width compression for mixed-mode BIST

A methodology to design efficient BIST test pattern generators

Configuring flip-flops to BIST registers

Hierarchical Test Compression for SoC Designs

Low cost BIST for EDAC circuits

Pseudorandom testing for boundary-scan design with built-in self-test

Two-dimensional test data decompressor for multiple scan designs

Test width compression for built-in self testing