NDLI: MCM compute node thermal failure-design or test problem?

Please wait, while we are loading the content...

2015 IEEE International Test Conference (ITC)

2014 International Test Conference

2013 IEEE International Test Conference (ITC)

2012 IEEE International Test Conference

2011 IEEE International Test Conference

2010 IEEE International Test Conference

2009 International Test Conference

2008 IEEE International Test Conference

2007 IEEE International Test Conference

2006 IEEE International Test Conference

IEEE International Conference on Test, 2005.

2004 International Conferce on Test

International Test Conference, 2003. Proceedings. ITC 2003.

Proceedings. International Test Conference

Proceedings International Test Conference 2001 (Cat. No.01CH37260)

Proceedings International Test Conference 2000 (IEEE Cat. No.00CH37159)

International Test Conference 1999. Proceedings (IEEE Cat. No.99CH37034)

Proceedings International Test Conference 1998 (IEEE Cat. No.98CH36270)

Proceedings International Test Conference 1997

Proceedings International Test Conference 1996. Test and Design Validity

Proceedings International Test Conference 1996. Test and Design Validity

Test generation for ultra-large circuits using ATPG constraints and test-pattern templates

Test pattern generation for circuits with asynchronous signals based on scan

Accelerated compact test set generation for three-state circuits

Comparing topological, symbolic and GA-based ATPGs: an experimental approach

BIST fault diagnosis in scan-based VLSI environments

LFSR reseeding as a component of board level BIST

Using ILA testing for BIST in FPGAs

An effective BIST scheme for datapaths

Four multi probing test for 16 bit DAC with vertical contact probe card

A demonstration IC for the P1149.4 mixed signal test standard

High-speed I/sub DDQ/ measurement circuit

Extending calibration intervals

Manufacturing test of fibre channel communications cards and optical subassemblies

A universal technique for accelerating simulation of scan test patterns

On potential fault detection in sequential circuits

Improving gate level fault coverage by RTL fault grading

Distributed mixed level logic and fault simulation on the Pentium/sup (R/)Pro microprocessor

Altering a pseudo-random bit sequence for scan-based BIST

MFBIST: a BIST method for random pattern resistant circuits

Two-dimensional test data decompressor for multiple scan designs

Mixed-mode BIST using embedded processors

Test quality of asynchronous circuits: a defect-oriented evaluation

Optimal scan for pipelined testing: an asynchronous foundation

An asynchronous scan path concept for micropipelines using the bundled data convention

Synthesis-for-initializability of asynchronous sequential machines

Burn-in elimination of a high volume microprocessor using I/sub DDQ/

IDDQ and AC scan: the war against unmodelled defects

High resolution I/sub DDQ/ characterization and testing-practical issues

Novel optical probing system with submicron spatial resolution for internal diagnosis of VLSI circuits

An exact non-enumerative fault simulator for path-delay faults

A diagnostic ATPG for delay faults based on genetic algorithms

Diagnostic fault equivalence identification using redundancy information and structural analysis

Self-learning signature analysis for non-volatile memory testing

Weak write test mode: an SRAM cell stability design for test technique

A built-in self-test circuit with timing margin test function in a 1 Gbit synchronous DRAM

Analog/digital testing of loaded boards without dedicated test points

Opens board test coverage: when is 99% really 40%?

A roadmap for boundary-scan test reuse

Local transformations and robust dependent path delay faults

On cancelling the effects of logic sharing for improved path delay fault testability

Detecting delay flaws by very-low-voltage testing

Testability features for a submicron voice-coder ASIC

A BIST Methodology for Comprehensive Testing of RAM with Reduced Heat Dissipation

Testing the digital modulation of PHS devices

Testing and characterizing jitter in 100BASE-TX and 155.52 Mbit/s ATM devices with a 1 Gsamples/s AWG in an ATE system

A BIST methodology for comprehensive testing of RAM with reduced heat dissipation

DFT strategy for Intel microprocessors

Proposal to simplify development of a mixed signal test standard

A method of extending an 1149.1 bus for mixed-signal testing

Early capture for boundary scan timing measurements

Identification and test generation for primitive faults

Test generation for global delay faults

ATPD: an automatic test pattern generator for path delay faults

Scan design oriented test technique for VLSI's using ATE

Virtual test of noise and jitter parameters

A novel approach to the analysis of VLSI device test programs

Digital integrated circuit testing using transient signal analysis

Towards an effective I/sub DDQ/ test vector selection and application methodology

Correlating defects to functional and I/sub DDQ/ tests

Defect-oriented vs schematic-level based fault simulation for mixed-signal ICs

Hierarchy based statistical fault simulation of mixed-signal ICs

An integration of memory-based analog signal generation into current DFT architectures

Partial scan design based on state transition modeling

A global algorithm for the partial scan design problem using circuit state information

Partial scan flip flop selection for simulation-based sequential ATPGs

Standard test interface language (STIL) a new language for patterns and waveforms

LIMSoft: automated tool for design and test integration of analog circuits

Developing a Testing Maturity Model for software test process evaluation and improvement

ASIC yield estimation at early design cycle

Risk assessment sampling plans for non-standard (maverick) material

SPC on the IC-production test process

Beyond the byzantine generals: unexpected behavior and bridging fault diagnosis

Defect-oriented IC test and diagnosis using VHDL fault simulation

Using target faults to detect non-target defects

A unifying methodology for intellectual property and custom logic testing

Constructive multi-phase test point insertion for scan-based BIST

Orthogonal scan: low overhead scan for data paths

An application of photoconductive switch for high-speed testing

Generation technique of 500 MHz ultra-high speed algorithmic pattern

The effect of period generation techniques on period resolution and waveform jitter in VLSI test systems

Analysis and detection of timing failures in an experimental Test Chip

A unique methodology for at-speed test of cDSP/sup TM/ and ASIC devices

Cost effective frequency measurement for production testing: new approaches on PLL testing

Backplane interconnect test in a boundary-scan environment

Testability-oriented hardware/software partitioning

System level fault simulation

ASIC BIST synthesis: a VHDL approach

Integrating scan into hierarchical synthesis methodologies

Synthesis of self-testing finite state machines from high-level specification

Fault coverage analysis for physically-based CMOS bridging faults at different power supply voltages

Realistic faults mapping scheme for the fault simulation of integrated analogue CMOS circuits

Iddq test: sensitivity analysis of scaling

Effects of multi-product, small-sized production of LSIs packaged in various packages on the final test process efficiency and cost

Issues in optimizing the test process-a Telecom case study

Application of boundary scan in a fault tolerant computer system

Optimal multiple chain relay testing scheme for MCMs on large area substrates

Three different MCMs, three different test strategies

MCM compute node thermal failure-design or test problem?

Commercial design verification: methodology and tools

Formal verification of the UltraSPARC/sup (TM)/ family of techniques

PowerPC/sup (TM)/ array verification methodology using formal techniques

An ATPG-based framework for verifying sequential equivalence

A unified framework for design validation and manufacturing test

From specification validation to hardware testing: a unified method

Testing-based analysis of real-time system models

Generation of test cases for hardware design verification of a super-scalar Fetch Processor

Process aggravated noise (PAN): new validation and test problems

ITC 1996 Lecture Series on Unpowered Opens Testing

Capacitive leadframe testing

High fault coverage of in-circuit IC pin faults with a vectorless test technique using parasitic transistors

Two new techniques for identifying opens on printed circuit boards: analog, junction test, and radio frequency induction test

Analog AC harmonic method for detecting solder opens

Unpowered opens test with X-ray laminography

An overview of CMOS VLSI failure analysis and the importance of test and diagnostics

Modelling the unmodellable: algorithmic fault diagnosis

Shmoo plotting: the black art of IC testing

Integrating automated diagnosis into the testing and failure analysis operations

IC failure analysis tools and techniques-magic, mystery, and science

Practical issues of failure diagnosis and analysis in a fast cycle time environment

The key to concurrent engineering is design tools

The return of asynchronous logic

Asynchronous design: working the fast lane

Challenge of the 90's: testing CoreWare/sup (TM/) based ASICs

The need for complete system level test standardization

Deep sub-micron I/sub DDQ/ test options

Proceedings., International Test Conference

Proceedings of 1995 IEEE International Test Conference (ITC)

Proceedings International Test Conference 1992

Proceedings of IEEE International Test Conference - (ITC)

1991, Proceedings. International Test Conference

Proceedings. International Test Conference 1990

Proceedings. 'Meeting the Tests of Time'., International Test Conference

International Test Conference 1988 Proceeding@m_New Frontiers in Testing

MCM compute node thermal failure-design or test problem?

Content Provider	IEEE Xplore Digital Library
Author	Sayre, E.P.
Copyright Year	1996
Description	Author affiliation: North East Syst. Associates Inc., USA (Sayre, E.P.)
Abstract	This paper is a unique documentation of a MCM thermal failure due to inadequate signal integrity of the test fixture used for at-speed testing. An accurate SPICE model of the rest fixture and MCM was developed utilizing TDR techniques and analytical representations of the test fixture elements. The SPICE analysis showed clearly that impedance mismatches within the fixture components and MCM carrier and test socket caused a significant increase in the RMS driver current and produced a 33% increase in power dissipation in each MCM I/O driver. The additional dissipation, in conjunction with the elevated temperature test environment caused the thermal failures observed during at-speed testing.
Starting Page	834
Ending Page	838
File Size	433331
Page Count	5
File Format	PDF
ISBN	0780335414
ISSN	10893539
DOI	10.1109/TEST.1996.557144
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1996-10-20
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Fixtures SPICE Temperature Failure analysis Sockets Production System testing Impedance Power dissipation Voltage
Content Type	Text
Resource Type	Article
Subject	Applied Mathematics Electrical and Electronic Engineering

Central Library (ISO-9001:2015 Certified)
Indian Institute of Technology Kharagpur
Kharagpur, West Bengal, India | PIN - 721302

See location in the Map
03222 282435
Mail: support@ndl.gov.in

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in