NDLI: Identification and test generation for primitive faults

Content Provider	IEEE Xplore Digital Library
Author	Krstic, A. Kwang-Ting Cheng Chakradhar, S.T.
Copyright Year	1996
Description	Author affiliation: Dept. of Electr. & Comput. Eng., California Univ., Santa Barbara, CA, USA (Krstic, A.)
Abstract	We propose a new method to identify and test primitive faults in combinational circuits described as multi-level or two-level netlists. A primitive fault is a multiple path delay fault for which none of the single paths contained in the fault is robustly or non-robustly testable while the presence of the fault can degrade the circuit performance. Identification and testing of primitive faults is important for at least two reasons: (1) a large percentage of paths in production circuits remain untestable under the single-path delay fault model, (2) distributed manufacturing defects usually adversely affect more than one path and these defects can be detected only by analyzing multiple affected paths. The single-path delay faults contained in a primitive fault have to merge at some gate(s). Our methodology for identifying primitive faults can quickly (1) rule out a large number of gates as possible merging points for primitive faults, and (2) prune the combination of paths that can never belong long any primitive fault. Our identification procedure also finds a test for the fault. We present a complete algorithm for identifying and testing double path delay faults. This procedure can be extended to identify primitive faults consisting of three or more paths. Experimental results on several multi-level combinational benchmark circuits are included to demonstrate the usefulness of our technique.
Starting Page	423
Ending Page	432
File Size	1134929
Page Count	10
File Format	PDF
ISBN	0780335414
ISSN	10893539
DOI	10.1109/TEST.1996.557046
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1996-10-20
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Fault diagnosis Circuit faults Circuit testing Delay Combinational circuits Robustness Degradation Circuit optimization Production Virtual manufacturing
Content Type	Text
Resource Type	Article
Subject	Applied Mathematics Electrical and Electronic Engineering

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