NDLI: An exact non-enumerative fault simulator for path-delay faults

Content Provider	IEEE Xplore Digital Library
Author	Gharaybeh, M.A. Bushnell, M.L. Agrawal, V.D.
Copyright Year	1996
Description	Author affiliation: Dept. of Electr. & Comput. Eng., Rutgers Univ., Piscataway, NJ, USA (Gharaybeh, M.A.)
Abstract	The present an efficient path-delay fault (PDF) simulator that does not involve enumeration of paths. Our method calculates the exact fault coverage, and identifies all tested faults in any circuit with a large number of paths. We present a new data structure, called the Path-Status Graph (PSG), to efficiently hold the status of each PDP in the circuit, i.e., whether or not the PDF is tested. The key to this efficiency is in breaking the information into pieces and distributing it over the data structure and in retaining all or part of the reconverging fanout structure of the circuit in the PSG. Thus, an exponential number of PDFs can share the same piece of information. Using one thousand random tests, we simulated all of the approximately 10/sup 20/ PDFs in the circuit c6288 and determined that 4.4 billion faults were detected. This number is larger by over three orders of magnitude compared to what was possible with previously reported methods.
Starting Page	276
Ending Page	285
File Size	1104679
Page Count	10
File Format	PDF
ISBN	0780335414
ISSN	10893539
DOI	10.1109/TEST.1996.556972
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1996-10-20
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Circuit faults Circuit simulation Data structures Computational modeling Delay Circuit testing Fault detection Automatic testing Electrical fault detection Automatic test pattern generation
Content Type	Text
Resource Type	Article
Subject	Applied Mathematics Electrical and Electronic Engineering

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