NDLI: An efficient algorithm for dual-voltage design without need for level conversion

Content Provider	IEEE Xplore Digital Library
Author	Allani, M. Agrawal, V.
Copyright Year	2012
Description	Author affiliation: Auburn University, 200 Broun Hall, ECE Dept., Auburn, AL 36849 (Agrawal, V.) \|\| Intel Corporation, 1501 S. Mopac Expy., Suite 400, Austin, TX 78746 (Allani, M.)
Abstract	We propose a technique to use dual supply voltages in digital designs to reduce energy consumption. New algorithms are proposed for finding and assigning a lower voltage in a dual voltage design. Given a circuit and a supply voltage and an upper bound on the critical path delay, the first algorithm finds an optimal lower supply voltage and a second algorithm assigns that lower voltage to selected gates. A linear time algorithm described in the literature is used for computing slacks for all gates of the circuit for a given supply voltage. For the computed gate slacks and the lower supply voltage, all gates are divided into three groups such that no gate in the first group can be assigned the lower supply, all gates in the second group can be simultaneously set to lower supply while maintaining positive slack for every gate, and gates in the third group are assigned low voltage, iteratively, in selected subsets at a time. The gate slacks are recalculated after each such voltage assignment. Thus, the overall complexity of this reduced power dual voltage assignment procedure is $O(n^{2}).$ SPICE simulations of ISCAS'85 benchmark circuits using the 90-nm bulk CMOS technology results show up to 60% energy savings.
Starting Page	51
Ending Page	56
File Size	446134
Page Count	6
File Format	PDF
ISBN	9781457714924
ISSN	00942898
e-ISBN	9781457714931
DOI	10.1109/SSST.2012.6195150
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2012-03-11
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Logic gates Delay Low voltage Algorithm design and analysis Benchmark testing SPICE Inverters energy savings Dual-voltage design Clustered Voltage Scaling (CVS) gate slack critical path level converter topological constraints
Content Type	Text
Resource Type	Article

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