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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Ahmad, T.B. Ciesielski, M. |
| Copyright Year | 2014 |
| Description | Author affiliation: ECE Dept., Univ. of Massachusetts Amherst, Amherst, MA, USA (Ahmad, T.B.; Ciesielski, M.) |
| Abstract | Simulation of the RTL model is one of the first and mandatory steps of the design verification flow. Such a simulation needs to be repeated often due to the changing nature of the design in its early development stages and after consecutive bug fixing. Despite its relatively high level of abstraction, RTL simulation is a very time consuming process, often requiring nightly or week-long regression runs. In this work, we propose an original approach to accelerating RTL simulation that leverages parallelism offered by multi-core machines. However, in contrast to traditional, parallel distributed RTL simulation, the proposed method accelerates RTL simulation in temporal domain by dividing the entire simulation run into independent simulation slices, each to be run on a separate core. It is combined with fast simulation model at ESL level that provides the required initial state for each independent simulation slice. The paper describes the basic idea of the method and provides some initial experimental results showing its effectiveness in improving RTL simulation performance in an automated way. |
| Sponsorship | IEEE Comput. Soc. |
| Starting Page | 71 |
| Ending Page | 76 |
| File Size | 347193 |
| Page Count | 6 |
| File Format | |
| ISBN | 9781479945603 |
| e-ISBN | 9781479945580 |
| DOI | 10.1109/DDECS.2014.6868766 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2014-04-23 |
| Publisher Place | Poland |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Computational modeling Mathematical model Integrated circuit modeling Logic gates Multicore processing Hardware Load modeling Testbench Simulation Verfication RTL Verilog ESL C SystemC |
| Content Type | Text |
| Resource Type | Article |
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