NDLI: A 64-MHz∼640-MHz 64-phase clock generator

Content Provider	IEEE Xplore Digital Library
Author	Hong-Yi Huang Jen-Chieh Liu Shi-Jia Sun Cheng-Hao Fu Kuo-Hsing Cheng
Copyright Year	2014
Description	Author affiliation: Dept. of Electr. Eng., Nat. Taipei Univ., Taipei, Taiwan (Hong-Yi Huang; Shi-Jia Sun; Cheng-Hao Fu) \|\| Dept. of Electr. Eng., Nat. Central Univ., Chungli, Taiwan (Kuo-Hsing Cheng) \|\| Inf. & Commun. Res. Labs., Ind. Technol. Res. Inst., Hsinchu, Taiwan (Jen-Chieh Liu)
Abstract	This paper proposes a wide-range all-digital phase locked loop (ADPLL) utilizing a successive approximation register-controlled (SAR) architecture. A modified digital to voltage converter (DAC) is adopted to provide a wide supply voltage range for the voltage controlled oscillator (VCO) so that the power consumption of can be reduced and a wide frequency range can be operated. A differential VCO is invented for reducing the jitter. A test chip is implemented using a 0.18μm CMOS process with an area of $500×620um^{2}.$ The measured frequency range is from 64MHz to 640MHz. The p2p jitter is 20.5 ps and the rms jitter is 2.4 ps.
Sponsorship	IEEE Comput. Soc.
Starting Page	51
Ending Page	54
File Size	584338
Page Count	4
File Format	PDF
ISBN	9781479945603
e-ISBN	9781479945580
DOI	10.1109/DDECS.2014.6868762
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2014-04-23
Publisher Place	Poland
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Voltage-controlled oscillators Frequency control Voltage control Delays Radiation detectors Clocks Phase locked loops
Content Type	Text
Resource Type	Article

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