NDLI: On the feasibility of combining on-line-test and self repair for logic circuits

Content Provider	IEEE Xplore Digital Library
Author	Koal, T. Ulbricht, M. Engelke, P. Vierhaus, H.T.
Copyright Year	2013
Description	Author affiliation: Infineon Technol. AG, Neubiberg, Germany (Engelke, P.) \|\| Brandenburg Univ. of Technol. Cottbus, Brandenburg, Germany (Koal, T.; Ulbricht, M.; Vierhaus, H.T.)
Abstract	Integrated circuits and systems implemented by using nano-technologies show a combination of known and new faults effects, which affect their reliability and their operational life time, specifically in safety-critical applications. Transient fault effects such as single and multiple event upsets (SEUs and MEUs) require fast error detection and compensation. Permanent faults may occur due to early life time failures on one side and stress-induced rapid aging on the other hand. They need to be compensated by repair technologies, preferably using “fresh” resources for the replacement of faulty functional units. As self repair is typically not a fast process and requires extra time while the system is off-line, on-line fault compensation must also catch and handle permanent faults that occur during “hot” operation. If on-line-test and error compensation on one side and repair technologies on the other hand are implemented independently, the resulting overhead in redundant circuitry becomes prohibitively high. In the following paper we therefore introduce a new concept of logic design which can meet the essential demands at reasonable cost using a flexible allocation of redundancy.
Sponsorship	IEEE Comput. Soc.
Starting Page	187
Ending Page	192
File Size	304922
Page Count	6
File Format	PDF
ISBN	9781467361354
e-ISBN	9781467361361
e-ISBN	9781467361347
DOI	10.1109/DDECS.2013.6549814
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2013-04-08
Publisher Place	Czech Republic
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Circuit faults Maintenance engineering Tunneling magnetoresistance Transistors Redundancy Fault detection Transient analysis
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

Combining on-line fault detection and logic self repair

Combining fault tolerance and self repair in a virtual TMR scheme

Generic Self Repair Architecture with On-Line Fault Diagnosis

Virtual TMR Schemes Combining Fault Tolerance and Self Repair

Combining fault tolerance and self repair at minimum cost in power and hardware

Generic Self Repair Architecture with Multiple Fault Handling Capability

Stateful tmr for transient faults

Fault Tolerant ALU System

A fault tolerant response analyzer with self-error-correction capability

On the feasibility of combining on-line-test and self repair for logic circuits

Similar Documents

Combining on-line fault detection and logic self repair

Combining fault tolerance and self repair in a virtual TMR scheme

Generic Self Repair Architecture with On-Line Fault Diagnosis

Virtual TMR Schemes Combining Fault Tolerance and Self Repair

Combining fault tolerance and self repair at minimum cost in power and hardware

Generic Self Repair Architecture with Multiple Fault Handling Capability

Stateful tmr for transient faults

Fault Tolerant ALU System

A fault tolerant response analyzer with self-error-correction capability

On the feasibility of combining on-line-test and self repair for logic circuits