NDLI: Hardware architecture for the fast pattern matching

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2015 IEEE 18th International Symposium on Design and Diagnostics of Electronic Circuits & Systems

17th International Symposium on Design and Diagnostics of Electronic Circuits & Systems

2013 IEEE 16th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS)

2013 IEEE 16th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS) [Copyright notice]

Foreword to the 16th IEEE DDECS Symposium

Symposium committees

Table of contents

Hardware-Software Co-Visualization: Developing systems in the holodeck

Approximate computing for energy-efficient error-resilient multimedia systems

Creating options for 3D-SIC testing

Interpolation-based model checking for efficient incremental analysis of software

Cross-layer resilient system design

Hardware acceleration in computer networks

Fault-based attacks on cryptographic hardware

Exploring processor parallelism: Estimation methods and optimization strategies

On design of priority-driven load-adaptive monitoring-based hardware for managing interrupts in embedded event-triggered real-time systems

Area-speed efficient modular architecture for $GF(2^{m})$ multipliers dedicated for cryptographic applications

On the on-line functional test of the Reorder Buffer memory in superscalar processors

Fault collapsing of multi-conditional faults

Efficient automated speedpath debugging

A static analysis approach to data race detection in SystemC designs

Debugging HDL designs based on functional equivalences with high-level specifications

Design of stochastic Viterbi decoders for convolutional codes

10Gb/s inverter based cascode transimpedance amplifier in 40nm CMOS technology

Ultra-high bandwidth fully-differential three-stage operational amplifiers in 40nm digital CMOS

A GHz full-division-range programmable divider with output duty-cycle improved

An area efficient hardware architecture design for H.264/AVC intra prediction reconstruction path based on partial reconfiguration

Automatic synthesis of small AdaBoost classifier in FPGA

A low jitter delay-locked-loop applied for DDR4

Power analysis methodology for secure circuits

Towards hardware architecture for memory efficient IPv4/IPv6 Lookup in 100 Gbps networks

Extensible open-source framework for translating RTL VHDL IP cores to SystemC

Multiobjective evolution of approximate multiple constant multipliers

Hardware architecture for the fast pattern matching

Digital methods of offset compensation in 90nm CMOS operational amplifiers

Frequency injection attack on a random number generator

Embedded microcontroller system for PilsenCUBE picosatellite

Proton beam characterization at Oslo Cyclotron Laboratory for radiation testing of electronic devices

Enhanced fault-tolerant Network-on-Chip architecture using hierarchical agents

A system-level overview and comparison of three High-Speed Serial Links: USB 3.0, PCI Express 2.0 and LLI 1.0

A Multi-Credit Flow Control scheme for asynchronous NoCs

An indirect technique for estimating reliability of analog and mixed-signal systems during operational life

Intermediate frequency filter calibration method for radio frequency receivers in modern CMOS technologies

Numerical method for DC fault analysis simplification and simulation time reduction

Relocation of reconfigurable modules on Xilinx FPGA

On performance estimation of a scalable VLIW soft-core in XILINX FPGAs

On the feasibility of combining on-line-test and self repair for logic circuits

Yield-oriented energy and performance model for subthreshold circuits with V variations

VeSFET as an analog-circuit component

Efficient mixture preparation on digital microfluidic biochips

Composing data-driven circuits using handshake in the clock-synchronous domain

A don't care identification method for test compaction

Test pattern decompression in parallel scan chain architecture

Indoor energy harvesting using photovoltaic cell for battery recharging

Noise and linearity analysis of a frequency to voltage converter

Energy-aware software development for embedded systems in HW/SW co-design

External capacitorless low dropout linear regulator using cascode structure

FPGA based time-of-flight 3D camera characterization system

Error resilient OBDDs

Design of an S-band 0.35 µm AlGaN/GaN LNA using cascode topology

Assertion based verification using PSL-like properties in Haskell

Reliability-aware cross-layer custom instruction screening

Efficiency of oscillation-based BIST in 90nm CMOS active analog filters

FPGA architecture for fast floating point matrix inversion using uni-dimensional systolic array based structure

Redundancy algorithm for embedded memories with block-based architecture

Analysis and comparison of functional verification and ATPG for testing design reliability

Fault-Tolerant Reconfigurable Low-Power pseudoRandom number Generator

A new method for correcting time and soft errors in combinational circuits

MBIST for LEON3 processor core cache

Fault tolerant CAN bus control system implemented into FPGA

Improved design of the uninterruptable power supply unit for powering of network devices

Hybrid Mesh-Ring wireless NoC for multi-core system

Novel model calibration method based on differential evolution used for SCR model fitting

TTTC: Test technology technical council

2012 IEEE 15th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS)

14th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems

13th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems

2009 12th International Symposium on Design and Diagnostics of Electronic Circuits & Systems

2008 11th IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems

2007 IEEE Design and Diagnostics of Electronic Circuits and Systems

2006 IEEE Design and Diagnostics of Electronic Circuits and systems

Hardware architecture for the fast pattern matching

Content Provider	IEEE Xplore Digital Library
Author	Kastil, J. Kosar, V. Korenek, J.
Copyright Year	2013
Description	Author affiliation: Fac. of Inf. Technol., Brno Univ. of Technol., Brno, Czech Republic (Kastil, J.; Kosar, V.; Korenek, J.)
Abstract	As the speed of current computer networks increases, it is necessary to protect networks by security systems such as firewalls and Intrusion Detection Systems (IDS) operating at multigigabit speeds. As attacks on modern networks became more and more complex, it is necessity to detect attack placed not only in single packet but at the level of network flows. Pattern matching in the network flows is the time-critical operation of many modern IDS. Most of the regularly used patterns are described by the regular expression. This work describes advanced hardware architecture for the fast regular expression matching based on the perfect hashing. The proposed architecture is scalable and can achieve multigigabit throughput per network flow.
Sponsorship	IEEE Comput. Soc.
Starting Page	120
Ending Page	123
File Size	159449
Page Count	4
File Format	PDF
ISBN	9781467361354
e-ISBN	9781467361361
e-ISBN	9781467361347
DOI	10.1109/DDECS.2013.6549801
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2013-04-08
Publisher Place	Czech Republic
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Pattern matching Automata Throughput Hardware Clocks Computer architecture Context
Content Type	Text
Resource Type	Article

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