NDLI: Design optimization for low light CMOS image sensors readout chain

Content Provider	IEEE Xplore Digital Library
Author	Boukhayma, A. Peizerat, A. Dupret, A. Enz, C.
Copyright Year	2014
Description	Author affiliation: EPFL, Neuchatel, Switzerland (Enz, C.) \|\| LETI, CEA, Grenoble, France (Boukhayma, A.; Peizerat, A.; Dupret, A.)
Abstract	For a CIS readout chain based on 4T pixel, column amplification and CDS, we confirm that thermal noise can be reduced to be neglected compared to 1/f noise using parameters independent of the pixel design, namely column level gain, bandwidth control or correlated multiple sampling (CMS). Based on analytic noise calculation and simulation results using 180nm process, we show that CMS has no advantage over CDS for thermal noise reduction but offers slightly more 1/f noise reduction (about 20% less 1/f noise if high number of samples is used). 1/f and RTS noise originating from the in-pixel source follower transistor are reported to be the dominant noise sources in CIS readout chain. Based on analytic noise calculation, we demonstrate that, for a given CMOS process, the input referred 1/f noise is minimal for a unique pair of gate dimensions of the in-pixel source follower and we give its expression as a function of technological parameters.
Starting Page	241
Ending Page	244
File Size	918888
Page Count	4
File Format	PDF
ISBN	9781479948857
DOI	10.1109/NEWCAS.2014.6934028
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2014-06-22
Publisher Place	Canada
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Noise Transistors Logic gates Thermal noise Transient analysis Bandwidth Capacitance
Content Type	Text
Resource Type	Article

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