NDLI: Hot carrier stress effect on the performance of 65 nm CMOS low noise amplifier

Content Provider	IEEE Xplore Digital Library
Author	Yehao Shen Jaehong Lee Hyungcheol Shin
Copyright Year	2009
Description	Author affiliation: Inter-University Semiconductor Research Center (ISRC) and School of Electrical Engineering, Seoul National University, San 56-1, Shinlim-dong, Kwanak-gu, 151-742, Korea (Yehao Shen; Jaehong Lee; Hyungcheol Shin)
Abstract	The effects of hot carrier stress on the characteristics of NMOSFETs and low noise amplifier (LNA) in 65 nm CMOS technology are investigated. The method of determining the stress condition is explained to achieve the maximum substrate current where maximum damage is generated in NMOSFETs. The increase in threshold voltage caused by hot carriers leads to a drop in the biasing current of the transistors. These effects lead to a decrease in the transconductance and output conductance of the device. There is almost no change in the subthreshold swing, gate-source and gate-drain capacitances. In the LNA, a drop of the power gain, power consumption, figure of merit (FoM) and an increase of the noise figure have been observed after hot carrier stress. However, the hot carrier stress has no effect on the optimal width of the MOSFET in the LNA circuit.
Starting Page	249
Ending Page	252
File Size	336541
Page Count	4
File Format	PDF
ISBN	9781424429332
e-ISBN	9781424429349
DOI	10.1109/ICICDT.2009.5166305
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2009-05-18
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Hot carriers Stress Low-noise amplifiers MOSFETs CMOS technology Threshold voltage Transconductance Capacitance Energy consumption Noise figure
Content Type	Text
Resource Type	Article

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