NDLI: Power-aware multi-objective evolvable hardware system on an FPGA

Content Provider	IEEE Xplore Digital Library
Author	López, B. Valverde, J. de la Torre, E. Riesgo, T.
Copyright Year	2014
Description	Author affiliation: Center of Ind. Electron., Univ. Politec. de Madrid, Madrid, Spain (López, B.; Valverde, J.; de la Torre, E.; Riesgo, T.)
Abstract	Dynamic and Partial Reconfiguration (DPR) allows a system to be able to modify certain parts of itself during run-time. This feature gives rise to the capability of evolution: changing parts of the configuration according to the online evaluation of performance or other parameters. The evolution is achieved through a bio-inspired model in which the features of the system are identified as genes. The objective of the evolution may not be a single one; in this work, power consumption is taken into consideration, together with the quality of filtering, as the measure of performance, of a noisy image. Pareto optimality is applied to the evolutionary process, in order to find a representative set of optimal solutions as for performance and power consumption. The main contributions of this paper are: implementing an evolvable system on a low-power Spartan-6 FPGA included in a Wireless Sensor Network node and, by enabling the availability of a real measure of power consumption at run-time, achieving the capability of multi-objective evolution, that yields different optimal configurations, among which the selected one will depend on the relative “weights” of performance and power consumption.
Sponsorship	Soc. Adapt. Evolvable Hardw. Syst. (ADEVO)
Starting Page	61
Ending Page	68
File Size	519865
Page Count	8
File Format	PDF
ISBN	9781479953561
DOI	10.1109/AHS.2014.6880159
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2014-07-14
Publisher Place	UK
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Power demand Field programmable gate arrays Power measurement Hardware Filtering Arrays Random access memory Wireless Sensor Networks evolvable hardware dynamic and partial reconfiguration power-aware multi-objective evolution FPGAs
Content Type	Text
Resource Type	Article

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
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3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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