NDLI: Hardware realization of a low complexity fading filter for Multipath Rayleigh fading simulator

Content Provider	IEEE Xplore Digital Library
Author	Ozen, S. Toker, K.A. Arsal, A.
Copyright Year	2010
Description	Author affiliation: ¿zmir University, 35290, Turkey (Toker, K.A.) \|\| ¿zmir Institute of Technology, 35430, Turkey (Ozen, S.) \|\| Sabanci University, 34956 Istanbul, Turkey (Arsal, A.)
Abstract	A low-complexity high performance Rayleigh fading simulator, and its Field Programmable Gate Array (FPGA) implementation are presented. This proposed method is a variant of the method of filtering of the white Gaussian noise where the filter design is accomplished in the analog domain and transferred into digital domain. The proposed model is compared with improved Jakes' model [1], auto-regressive filtering [2] and IDFT [3] techniques, in performance and computational complexity. Proposed method outperforms AR(20) filter and modified Jakes' generators in performance. Although IDFT method achieves the best performance, it brings a significant cost in storage and is undesirable. The proposed method achieves high performance with the lowest complexity, and its performance has been verified on Virtex4 and Spartan3e FPGA platforms. Our fixed-point Rayleigh fading-channel simulator utilizes only 2% of the configurable slices, 1% of the Look-Up-Table (LUT) resources and 3% of the dedicated multipliers on a Xilinx Virtex4 - xc4vsx35 FPGA platform.
Starting Page	1
Ending Page	5
File Size	5677597
Page Count	5
File Format	PDF
ISBN	9781424466887
e-ISBN	9781424466894
DOI	10.1109/WAMICON.2010.5461896
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2010-04-12
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Rayleigh channels Hardware Field programmable gate arrays Digital filters Filtering Field programmable analog arrays Gaussian noise Computational complexity Costs Table lookup
Content Type	Text
Resource Type	Article

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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