NDLI: iScan: Indirect-access scan test over HOY test platform

Content Provider	IEEE Xplore Digital Library
Author	Chao-Wen Tzeng Chun-Yen Lin Shi-Yu Huang Chih-Tsun Huang Jing-Jia Liou Hsi-Pin Ma Po-Chiun Huang Cheng-Wen Wu
Copyright Year	2009
Description	Author affiliation: Dept. of Electrical Engineering, National Tsing Hua University, HsinChu, Taiwan (Chao-Wen Tzeng; Chun-Yen Lin; Shi-Yu Huang; Jing-Jia Liou; Hsi-Pin Ma; Po-Chiun Huang; Cheng-Wen Wu) \|\| Dept. of Computer Science, National Tsing Hua University, HsinChu, Taiwan (Chih-Tsun Huang)
Abstract	In this paper, we introduce a new test paradigm called indirect-access scan test, demonstrated over the HOY test platform [12]. Unlike the traditional ATE-based testing, the test data in this paradigm are sent to the chip under test via packets over a single indirect channel. Although there is extra test time overhead for establishing the store-and-forward communication, it offers almost unlimited test memory - a highly desirable property since the large volume of test data today could easily blow up a traditional ATEs test memory. In addition to demonstrating the feasibility of this new paradigm, we also show that its efficiency can be substantially improved by two schemes; i.e., primary input (PI) data encoding and dynamic packet formatting. For a design with 155K gates, the speed-up achieved can be more than 50X.
Starting Page	60
Ending Page	63
File Size	258930
Page Count	4
File Format	PDF
ISBN	9781424427819
DOI	10.1109/VDAT.2009.5158095
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2009-04-28
Publisher Place	Taiwan
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Circuit testing Electronic equipment testing Integrated circuit testing Performance evaluation Contracts Communication system control Chaotic communication Computer science Pins Timing HOY Test Platform Scan Test Indirect-Access Testing Test Compression
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

Hierarchical test approach using boundary scan test

Test compaction in a parallel access scan environment

Enhanced reduced pin-count test for full-scan design

Boundary scan test solution for MorPACK platform

Impact Of Boundary-Scan Design On Delay Test

Using timing flexibility of automatic test equipment to complement X-tolerant test compression techniques

Interval Based X-Masking for Scan Compression Architectures

Reuse-based test access and integrated test scheduling for network-on-chip

The integration of boundary-scan test methods to a mixed-signal environment

iScan: Indirect-access scan test over HOY test platform

Similar Documents

Hierarchical test approach using boundary scan test

Test compaction in a parallel access scan environment

Enhanced reduced pin-count test for full-scan design

Boundary scan test solution for MorPACK platform

Impact Of Boundary-Scan Design On Delay Test

Using timing flexibility of automatic test equipment to complement X-tolerant test compression techniques

Interval Based X-Masking for Scan Compression Architectures

Reuse-based test access and integrated test scheduling for network-on-chip

The integration of boundary-scan test methods to a mixed-signal environment

iScan: Indirect-access scan test over HOY test platform