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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Pan Yu Mitra, T. |
| Copyright Year | 2007 |
| Description | Author affiliation: Nat. Univ. of Singapore, Singapore (Pan Yu; Mitra, T.) |
| Abstract | Extensible processors allow addition of application-specific custom instructions to the core instruction set architecture. These custom instructions are selected through an analysis of the program's dataflow graphs. The characteristics of certain applications and the modern compiler optimization techniques (e.g., loop unrolling, region formation, etc.) have lead to substantially larger dataflow graphs. Hence, it is computationally expensive to automatically select the optimal set of custom instructions. Heuristic techniques are often employed to quickly search the design space. In order to leverage full potential of custom instructions, our previous work proposed an efficient algorithm for exact enumeration of all possible candidate instructions (or patterns) given the dataflow graphs. But the algorithm was restricted to connected computation patterns. In this paper, we describe an efficient algorithm to generate all feasible disjoint patterns starting with the set of feasible connected patterns. Compared to the state-of-the-art technique, our algorithm achieves orders of magnitude speedup while generating the identical set of candidate disjoint patterns. |
| Starting Page | 273 |
| Ending Page | 278 |
| File Size | 252430 |
| Page Count | 6 |
| File Format | |
| ISBN | 9781424410590 |
| DOI | 10.1109/FPL.2007.4380659 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2007-08-27 |
| Publisher Place | Netherlands |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Computer aided instruction Application specific integrated circuits Space exploration Scalability Computer science Computer architecture Application software Optimizing compilers Application specific processors Embedded computing subgraph enumeration algorithm ASIPs customizable processors custom instruction instruction-set extensions |
| Content Type | Text |
| Resource Type | Article |
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